PROJECT

COMMAND MODULE

APOLLO

GUIDANCE AND NAVIGATION SYSTEM MANUAL

VOLUME II

r

ND -1021041

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* !

REV LETTER ON VOL I

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APOLLO

COMMAND MODULE

BLOCK I SERIES 100

GUIDANCE AND

NAVIGATION SYSTEM MANUAL

VOLUME II OF II

PREPARED FOR

NATIONAL AERONAUTICS AND SPACE ADMINISTRATION MANNED SPACECRAFT CENTER

BY

AC ELECTRONICS DIVISION OF GENERAL MOTORS Q MILWAUKEE,WISCONSIN 53201

I

NASA CONTRACT NAS 9-497

1

APOLLO GUIDANCE AND NAVIGATION SYSTEM

ND-1021041

MANUAL

CONTENTS

Chapter Page

Volume II

4 (cont) 4-8.6 Memory . 4-309

4-8.7 Power Supply . 4-375

4-8.8 Machine Instructions . 4-388

4-8.9 Programs . 4-472

4- 9 Display and Keyboards (DSKY' s) . 4-491

4-9.1 AGC Main Panel DSKY Functional Description . 4-491

4-9.2 AGC Main Panel DSKY Detailed Description . 4-493

4-9.3 AGC Navigation Panel DSKY Functional Description. . . 4-515

4- 9.4 AGC Navigation Panel DSKY Detailed Description .... 4-515

5 PRE-LAUNCH AND IN-FLIGHT OPERATIONS . 5-1

5- 1 Scope . 5-1

5-2 Preparation for Launch . 5-1

5- 2. 1 Prelaunch IMU Alignment . 5-1

5-3 Boost Phase . 5-3

5-4 Orbital Navigation . 5-3

5-4. 1 Star-Horizon Navigational Measurement . 5-4

5-4.2 Landmark Navigational Measurement . 5-5

5-5 In-flight IMU Alignments . 5-5

5-6 Thrust Maneuvers . 5-7

5-7 Entry . 5-8

6 CHECKOUT AND MAINTENANCE EQUIPMENT . 6-1

6- 1 Scope . 6-1

7 CHECKOUT . 7-1

7- 1 Scope . 7-1

7-2 G and N System . 7-1

7-2.1 Preparation . 7-1

7-2.2 Checkout . . 7-1

7 -3 Inertial Subsystem (ISS) . 7-18

7-3.1 Preparation . 7-18

7-3.2 Checkout . 7-18

7-4 Optical Subsystem (OSS) . 7-19

7-4.1 Preparation . 7-19

7-4.2 Checkout . 7-19

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CONTENTS (cont)

Chapter Page

7- 5 Computer Subsystem (CSS) . 7-19

7-5.1 Preparation . 7-19

7- 5.2 Checkout . 7-19

8 MAINTENANCE . 8-1

8- 1 Scope . 8-1

8-2 G and N System . 8-1

8- 2. 1 Maintenance Concept . 8-1

8-2.2 Malfunction Isolation . 8-2

8-2.3 Black Box Double Verification . 8-5

8-2.4 Pre-Installation Acceptance Test (PIA) . 8-5

8-2.5 Removal and Replacement . 8-6

8-3 Inertial Subsystem . 8-6

8-3.1 Maintenance Concept . 8-6

8-3.2 Malfunction Isolation . 8-6

8-3.3 Black Box Double Verification . 8-11

8-3.4 Repair Verification . 8-12

8-3.5 Pre-Installation Acceptance Test . 8-12

8-3.6 Removal and Replacement . 8-12

8-4 Optical Subsystem . 8-12

8-4.1 Maintenance Concept . 8-12

8-4.2 Malfunction Isolation . 8-13

8-4.3 Black Box Double Verification . 8-13

8-4.4 Repair Verification . 8-13

8-4.5 Pre-Installation Acceptance Test . 8-13

8-4.6 Removal and Replacement . 8-13

8-4.7 Optical Cleaning . 8-13

8-5 Computer Subsystem . 8-16

8-5.1 Maintenance Concept . 8-16

8-5.2 Malfunction Isolation . 8-17

8-5.3 Black Box Double Verification . 8-17

8-5.4 Repair Verification . 8-17

8-5.5 Pre-Installation Acceptance Test . 8-17

8-5.6 Removal and Replacement . 8-17

8-5.7 Maintenance Schedule . 8-18

APPENDIX A List of Technical Terms and Abbreviations . A-l

APPENDIX B Related Documentation . B-l/B-2

APPENDIX C Logic Symbols . C-l

Il-iv

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ILLUSTRATIONS

Figure Page

Volume II

4-148 Erasable Memory, Functional Diagram . 4-311/4-312

4-149 Erasable Memory, Timing Diagram . 4-314

4-150 X and Y Selection, Simplified Diagram . 4-316

4-151 Core Array . 4-318

4-152 Bit Plane . 4-319

4-153 Memory Cycle Timing - Erasable . 4-321/4-322

4-154 X and Y Coordinates . 4-323

4-155 Address Decoder . 4-325/4-326

4-156 Selection Switches and Drivers . 4-329/4-330

4-157 Inhibit Line Drivers . 4-333/4-334

4-158 Sense Amplifier and Voltage Source . 4-335/4-336

4-159 Strobe Driver . 4-338

4-160 Fixed Memory, Functional Diagram . 4-339/4-34C

4-161 Rope Module . 4-341

4-162 Fixed Memory Cycle, Timing Diagram . 4-341

4-163 Rope Organization . 4-343/4-344

4-164 Rope Module Organization . 4-347/4-348

4-165 Memory Cycle Timing . 4-351/4-352

4-166 Bank Register . 4-353/4-354

4-167 Bank Selector Gates . 4-359/4-360

4-168 Set Selector Gates . 4-361

4-169 Inhibit Gates . 4-363

4-170 Strand Gates . 4-364

4-171 Rope and Strand Selectors . 4-365/4-366

4-172 Fixed Memory Inhibit Drivers and Return Circuits . 4-369/4-370

4-173 Fixed Memory Set Drivers and Return Circuits . 4-371/4-372

4-174 Fixed Memory Reset Drivers and Return Circuits . 4-373/4-374

4-175 Sense Amplifier and Voltage Source . 4-377/4-378

4-176 Power Supply, Functional Block Diagram . 4-379/4-380

4-177 Primary Power Filter . 4-381

4-178 +3 Volt Power Supply . 4-383/4-384

4-179 +13 Volt Power Supply . 4-385/4-386

4-180 Stanbdy Circuit . 4-387

4-181 Power Supply Filter Circuits . 4-389/4-390

4-182 Power Supply Failure Detection Circuits . 4-391/4-392

4-183 Subinstruction STD2 (Example for z ^ 0020) . 4-399

4-184 Subinstruction STD2 (Example for z = 0001) 4-407

4-185 Subinstruction TC0 . 4-409

4-186 Subinstruction XCH0 . 4-411

4-187 Subinstruction CS0 . 4-413

4-188 Subinstruction TS0 (without Overflow or Underflow in A) . 4-414

4-189 Subinstruction TS0 (with Overflow or Underflow in A) . 4-415

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ILLUSTRATIONS (cont)

Figure Page

4-190 Subinstruction MSKO . 4-417

4-191 Subinstruction ADO . 4-418

4-192 Subinstruction NDXO . 4-420

4-193 Subinstruction NDXI . 4-421

4-194 Subinstruction CCSO (Example e> + 0) . 4-423

4-195 Subinstruction CCSO (Example e = + 0) . 4-424

4-196 Subinstruction CCSO (Example e< + 0) . 4-425

4-197 Subinstruction CCSO (Example e = - 0) . 4-426

4-198 Subinstruction CCS1 . 4-427

4-199 Subinstruction SUO . 4-429

4-200 Multiplication of Two Binary Numbers, Principle of Operation .... 4-430

4-201 Multiplication of Two Binary Numbers, Method of Operation . 4-432

4-202 Subinstruction MP0 (a and e Positive) . 4-433

4-203 Subinstruction MP0 (a Positive and e Negative) . 4-434

4-204 Subinstruction MP0 (a and e Negative) . 4-435

4-205 Subinstruction MP0 (a Negative and e Positive) . 4-436

4-206 Subinstruction MP1 . 4-437

4-207 Subinstruction MP3 . 4-438

4-208 Division of Binary Numbers, Principle of Operation . 4-443

4-209 Division of Binary Numbers, Method of Operation . 4-445

4-210 Subinstruction DV0 (a and e Positive) . 4-447

4-211 Subinstruction DV0 (a Positive and e Negative) . 4-448

4-212 Subinstruction DV0 (a Negative and e Positive) . 4-449

4-213 Subinstruction DV0 (a and e Negative) . 4-450

4-214 Subinstruction DV1 (Incorrect Remainder) . 4-451

4-215 Subinstruction DV1 (Correct Remainder) . 4-452

4-216 Subinstruction RPT1 . 4-461

4-217 Subinstruction RPT3 . 4-462

4-218 Subinstruction RSM . 4-464

4-219 Subinstruction PINC . . 4-465

4-220 Sub instruction MENC . 4-467

4-221 Subinstruction SHINC . 4-468

4-222 Completion of an Uplink Word . 4-469

4-223 Subinstruction SHANC . 4-471

4-224 Subinstruction OINC . 4-473

4-225 Subinstruction LINC . 4-474

4-227 DSKY’s, Functional Diagram . 4-492

4-228 AGC Main Panel DSKY . 4-494

4-229 AGC Main Panel DSKY, Schematic Diagram . 4-495/4-496

4-230 Decoder, AGC Main Panel DSKY . 4-499/4-500

4-231 Relay Matrix, AGC Main Panel DSKY . 4-501/4-502

4-232 Display Locations, AGC Main Panel DSKY . 4-506

4-233 Relay Matrix Display Connections . 4-507/4-508

4-234 G and N System and Spacecraft Relay Functions, AGC

Main Panel DSKY . 4-511/4-512

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ILLUSTRATIONS (cont)

Figure Page

4-235 Alarm Circuits, AGC Main Panel DSKY . 4-513/4-514

4-236 Power Supply, AGC Main Panel DSKY . 4-516

4-237 AGC Navigation Panel DSKY . 4-518

4-238 AGC Navigation Panel DSKY, Schematic Diagram . 4-519/4-520

4-239 Decoder, AGC Navigation Panel DSKY . 4-521/4-522

4-240 Relay Matrix, AGC Navigation Panel DSKY . 4-523/4-524

4-241 G & N System Relay Functions, AGC Navigation Panel DSKY . . 4-525/4-526

4-242 Display Locations, AGC Navigation Panel DSKY . 4-527

4- 243 Alarm Circuits, AGC Navigation Panel DSKY . 4-529/4-530

5- 1 Flight Profile for Earth Orbiting Mission . 5-2

5-2 Prelaunch IMU Alignment . 5-3

5-3 Star-Horizon Navigational Measurement . 5-4

5-4 Orbital Navigation Sighting . 5-6

5-5 In-flight IMU Alignment . 5-7

5- 6 Command Module Entry Attitude . 5-9/5-10

6- 1 Universal Test Station Layout . 6-12

7- 1 G and N System Checkout Master Flowgram . 7-37/7-38

7-2 G and N System Checkout Preparation Flowgram . 7-39/7-40

7-3 G and N System Checkout Flowgram . 7-41/7-42

7-4 ISS Checkout Master Flowgram . 7-43/7-44

7-5 ISS Checkout Preparation Flowgram . 7-45/7-46

7-6 ISS Checkout Flowgram . 7-47/7-48

7-7 OSS Checkout Master Flowgram . 7-49/7-50

7-8 OSS Checkout Preparation Flowgram . 7-51/7-52

7-9 OSS Checkout Flowgram . 7-53/7-54

7-10 CSS Checkout Master Flowgram . 7-55

7-11 CSS Checkout Preparation Flowgram . 7-56

7-12 CSS Program Checkout Flowgram . 7-57

7- 13 CSS Functional Checkout Flowgram . 7-58

8- 1 G and N System and Subsystem Maintenance Concept Flowgram • • 8-3/8-4

C-l NOR Gate Symbols . C-2

C-2 NOR Gate Schematic . C-4

C-3 NOR Gate Flip-Flop . C-5

C-4 Logic Diagram Symbols . C-6

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MANUAL

TABLES

Number Page

Volume II

4-XH Addressing . 4-313

4-XIH Register S Bit Assignments . 4-324

4-XIV Addressing . 4-349/4-350

4-XV Bank Addressing . 4-356

4-XVI Selector Gates - Inputs and Outputs . 4-361

4 -XVII Strand Gate Input and Output Signals . 4-362

4-XVni Rope and Strand Selection Signals . 4-368

4-XIX Machine Instructions . 4-393

4-XX Control Pulses . 4-395

4-XXI Control Pulse Timing for all Machine Instructions . 4-401

4 -XXII Contents of A and Z at End of CCSO and CCS1 . 4-422

4-XXin Contents of Registers at End of MPO . 4-440

4-XXIV Contents of Registers at End of DVO . 4-454

4-XXV RUPT Transfer Routines . 4-459

4-XXVI Program Sunrise 45 — Program Sections . 4-476

4-XXVII Keys and Keycode . 4-497

4-XXVm Display Codes . 4-504

4-XXIX Digit Code . 4-505

4-XXX Relay Matrix Codes . 4-528

6-1 Checkout and Maintenance Test Equipment . 6-2

6-n Checkout and Maintenance Tools . 6-7

6- m List of Operating Procedure JDC ?s for GSE . 6-7

7- 1 Equipment Required for Checkout . 7-20

7-H G and N System Interconnect Cables . 7-25

7-m Inertial Subsystem Interconnect Cables . 7-28

7-IV Optical Subsystem Interconnect Cables . 7-33

7- V Computer Subsystem Interconnect Cables . 7-36

8“I ISS Schematics . 8-7

8- n OSS Loop Diagrams and Schematics . 8-14

8-in CSS Logic Diagrams and Schematics . 8-18

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APOLLO GUIDANCE AND NAVIGATION SYSTEM

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MANUAL

4-8.6 MEMORY. Memory consists of an erasable memory with a storage capacity of 1024 words and a fixed core rope memory. Erasable memory is a random-access, destructuve readout storage device. Data stored in erasable memory can be altered or updated. Fixed memory is a nondestructive storage device. Data stored in fixed memory is unalterable since the data is wired in.

Both memories contain magnetic-core storage elements. In erasable memory the storage elements form a core array; in fixed memory the storage elements form three core ropes. Erasable memory has a density of one word per 16 cores; fixed memory has a density of eight words per core. Each word is located by an address.

Addresses are assigned to instructions to specify the sequence in which they are to be executed, and blocks of addresses are reserved for data such as constants and tables. The information is then put into assigned locations in erasable memory with the CTS, the DSKY’s, uplink, or program operation. Information is placed into fixed memory permanently by wiring patterns through the magnetic cores.

A common address register (register S) in the central processor is used with both memories. When register S contains an address pertaining to erasable memory, the erasable memory cycle timing is energized. Timing pulses sent to the erasable mem¬ ory cycle timing then produce strobe signals for the read, write, and sense functions. The address decoder receives addresses from register S and produces selection signals for the core array. The selection signals allow a word to be written into or read out of the selected storage location. The selected word is strobed by the strobe signals and applied to the sense amplifiers. The sense amplifiers are also strobed and the word is entered into the memory buffer register (G) in the central processor.

Fixed memory contains an addition address register (bank register) which is necessary because of the increased number of locations. Register S addresses ener¬ gize the fixed memory cycle timing when a location in fixed memory is addressed. The timing pulses sent to the fixed memory cycle timing produce the strobe signals for the read and sense functions. The selection logic receives addresses from regis¬ ters S and the bank register (register BNK) and produces selection signals for the core ropes. Register BNK receives addresses from the centrol processor write lines when the register is addressed and when the proper control pulses from the sequence generator are present. The content of a storage location in fixed memory is strobed from the fixed memory sense amplifiers, through the sense amplifiers in erasable memory, and into register G in the central processor.

4"8-6-1 Erasable Memory Functional Description. Erasable (E) memory (figure 4-148) consists of a core array, memory cycle timing circuits, the address decoder, selection circuits, and sense amplifiers. The core array is the storage medium by which data is stored in erasable memory. The memory cycle timing circuits generate strobe signals which enable the selection circuits and the sense amplifiers. The address decoder con¬ verts the contents of register S into X and Y selection signals for addressing a storage location. The selection circuits select the addressed storage location under control of the selection signals from the address decoder and strobe signals from the memory cycle timing circuits. The sense amplifiers detect the contents of the selected storage location and supply this data to register G.

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Erasable memory is addressed by the contents of register S, provided bits 11 and 12 are both logic ZERO'S. (See table 4-XII) Only 1008 of a possible 1024 storage lo¬ cations are utilized by erasable memory. The first 14 locations are reserved for the addressable flip-flop registers and are assigned octal addresses 0000 through 0015. Address 0016 and 0017 have no assigned location; these addresses are used by pro¬ gram to inhibit and release the inhibit of interrupt requests.

4-8.6. 1.1 Core Array. The core array has 1024 word storage locations, contained in 16 bit planes and defined by the intersection of 32 X lines and 32 Y lines. Each bit plane contains 1024 cores. An individual bit in each plane is selected by the intersec¬ tion of an X and Y line threading a core. The selection signals are generated by the address decoder subject to strobe signals from erasable memory cycle timing cir¬ cuits. This occurs simultaneously in all 16 bit planes thus selecting one word storage location. Each core is also threaded by a sense line and an inhibit line. The sense line threads all cores in a particular bit plane, such that current is induced into the senseline if the state of any core in the plane is changed from ONE to a ZERO. Cur¬ rent through the inhibit line prevents any core in the bit plane from switching since it opposes the current on the X and Y selection lines. Thus, current on a combination of X, Y, and inhibit lines determines which cores are selected. Core selection is identical for both the read and write operations.

4-8. 6. 1.2 Erasable Memory Cycle Timing Circuits. The erasable memory cycle timing circuits consist of timing control and timing flip-flops, which generate strobe signals to sequence the operation of erasable memory. These strobe signals are generated during one memory cycle time (11.7 microsecond), subject to timing signals from the timer as shown in figure 4-149. The timing control generates the strobe signals subject to signal FER. Signal FER is generated only when bits 11 and 12 of register S are both logic ZERO'S, signal MC is present, and signal SCAD is not present. Bits 11 and 12 are logic ZERO'S when the specified memory address is lower than 2000 (octal), which indicates that either an addressable register or erasable memory has been addressed. Signal MC is present, provided that a multiply or divide instruction is not in progress or signal GOJAM has not been initiated. Signal SCAD is a logic ONE when the specified address is lower than 0020 (this address indicates one of the addressable registers is being addressed). The timing control also generates signal TIMR when either signal STOP A (indicating a monitor stop) or signal STOP B (indicating an alarm) is present. Signal TIMR resets several timing flip-flops in erasable memory and inhibits the addressing of the ropes in fixed memory. Input MYCLMP inhibits access to memory (and avoids any loss of data) if the 3 volt power supply falls out of limits.

The timing flip-flops generate the various strobe signals which enable the selec¬ tion circuits and sense amplifiers. The strobe signals generated are read, set, reset, write, inhibit, and sense. As previously discussed, several strobe signals are inhib¬ ited by signal TIMR; the remaining strobe signals are inhibited by signal GOJAM. Therefore, these two signals inhibit access to erasable and fixed memory when a mon¬ itor stop has been initiated by the CTS or when an alarm condition has occurred within the AGC.

4-310

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[address decoder]

Figure 4-148. Erasable Memory, Functional Diagram

4-311/4-312

APOLLO GUIDANCE AND NAVIGATION SYSTEM

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MANUAL

Table 4-XII. Addressing

Register Groups	Octal Address	Pseudo Address (Decimal)	Contents ot BNK “	Contents o( S *
Real	Pseudo	15	14	13	12	11	12	11	10	9	8	7	6	5	4	3	2	1
CP	A Q. Z. LP	0000 0003	Same	0 3	X	X	X	X	X	0	0	0	0	0	0	0	0	0	0	X	X
IN	0004 • 0007	Same	4 7	X	X	X	X	X	0	0	0	0	0	0	0	0	0	1	X	X
OUT	0010 0014	Same	8 12	X	X	X	X	X	0	0	0	0	0	0	0	0	1	X	X	X
BNK	0015	Same	13	X	X	X	X	X	0	0	0	0	0	0	0	0	1	1	0	1
	No Bit Location	0016 • 0017	Same	14. 15	X	X	X	X	X	0	0	0	0	0	0	0	0	1	1	1	X
E	Special	0020 0027	Same	16 23	X	X	X	X	X	0	0	0	0	0	0	0	1	0	X	X	X
Spares	0030 0033	Same	24 27	X	X	X	X	X	0	0	0	0	0	0	0	1	1	0	X	X
CTR	0034 0057	Same	28 - 47	X	X	X	X	X	0	0	0	0	0	0	X	X	X	X	X	X
	GE		0060 1777	Same	48 1023	X	X	X	X	X	0	0	X	X	X	X	X	X	X	X	X	X
F	ri	FF	BANK 01	2000 ■ 3777	Same	1024 2047	X	X	X	X	X	0	1	X	X	X	X	X	X	X	X	X	X
0?	4000 5777	Same	2048 3071	X	X	X	X	X	1	0	X	X	X	X	X	X	X	X	X	X
FS	03	6000 7777	6000 7777	3072 ■ 4095	0	0	0	X	X	1	1	X	X	X	X	X	X	X	X	X	X
04	6000 7777	10000 11777	4096 ■ 5119	0	0	1	0	0	1	1	X	X	X	X	X	X	X	X	X	X
05	6000 7777	12000 13777	5120- 6143	0	0	1	0	1	1	l	X	X	X	X	X	X	X	X	X	X
06	6000 7777	14000 ■ 15777	6144 7167	0	0	1	1	0	1	1	X	X	X	X	X	X	X	X	X	X
07	6000 7777	16000 - 17777	7168 8191	0	0	1	1	1	1	1	X	X	X	X	X	X	X	X	X	X
10	6000 7777	20000 21777	8192 9215	0	1	0	0	0	1	1	X	X	X	X	X	X	X	X	X	X
F2	11	6000 7777	22000 23777	9216 10239	0	1	0	0	1	1	1	X	X	X	X	X	X	X	X	X	X
12	6000 7777	24000 - 25777	10240 11263	0	1	0	1	0	1	1	X	X	X	X	X	X	X	X	X	X
13	6000 7777	26000 27777	11264 12287	0	1	0	1	1	1	1	X	X	X	X	X	X	X	X	X	X
14	6000 7777	30000 31777	12288 13311	0	1	1	0	0	1	1	X	X	X	X	X	X	X	X	X	X
21	6000 7777	42000 - 43777	17408 18431	1	0	0	0	1	1	1	X	X	X	X	X	X	X	X	X	X
22	6000 7777	44000 45777	18432 19455	1	0	0	1	0	1	1	X	X	X	X	X	X	X	X	X	X
23	6000 7777	46000 47777	19456 20479	1	0	0	1	1	1	1	X	X	X	X	X	X	X	X	X	X
24	6000 7777	50000 51777	20480 21503	1	0	1	0	0	1	1	X	X	X	X	X	X	X	X	X	X
F3	25	6000 7777	52000 53777	21504 22527	1	0	1	0	1	1	1	X	X	X	X	X	X	X	X	X	X
26	6000 7777	54000 55777	22528 23551	1	0	1	1	0	1	1	X	X	X	X	X	X	X	X	X	X
27	6000 7777	56000 57777	23552 24575	1	0	1	1	1	1	1	X	X	X	X	X	X	X	X	X	X
30	6000 7777	60000 61777	24576 25599	1	1	0	0	0	1	1	X	X	X	X	X	X	X	X	X	X
31	6000 7777	62000 63777	25600 26623	1	1	0	0	1	1	1	X	X	X	X	X	X	X	X	X	X
32	6000 7777	64000 65777	26624 27647	1	1	0	1	0	1	1	X	X	X	X	X	X	X	X	X	X
33	6000 7777	66000 67777	27648 29671	1	1	0	1	1	1	1	X	X	X	X	X	X	X	X	X	X
34	6000 7777	70000 71777	28672 29695	1	1	1	0	0	1	1	X	X	X	X	X	X	X	X	X	X
" X means 0 or 1

068 7

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MANUAL

TOI T02 T03 T04 T05 T06 TOT T08 T09 TIO Til TI2 TOI T02 T03

SET PULSE (SETEK)

READ PULSE (REX AND REY)

SENSE STROBE ISBE)

RESET PULSE (RSTKX AND RSTKY)

INHIBIT PULSE (ZID)

WRITE PULSE (WEX AND WEY)

Figure 4-149. Erasable Memory, Timing Diagram

4-8.6. 1.3 Address Decoder. Bits 10 through 1 of register S contain the address of the location in erasable memory being interrogated. The address decoder (figure 4-148) receives this address and produces signals which select the addressed storage loca¬ tion. Since each bit in a 16 bit storage location is selected by the intersection of an X and a Y selection line, and there are 32 X planes and 32 Y planes, a signal is needed to select each combination. The selection is accomplished by two 4-by-8 matrices, one for the Y lines. The X selection signals, derived from bits 5 through 1 of register S, are XTO through XT3 and XBO through XB7. The Y selection signals, derived from bits 10 through 6 of register S, are YTO through YT3 and YBO through YB7. The XT and YT signals are supplied to the top select drivers, and the XB and YB signals are supplied to the bottom select drivers. In addition, the two sets of selection signals are combined to form addresses which are forwarded to fixed memory for addressing the bank register, to input-output control for controlling parity test, and to the central processor for addressing the addressable registers. Counter addresses are sent also to the priority control and the sequence generator.

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MANUAL

4-8. 6. 1.4 Selection Switches and Drivers. Selection signals from the address decoder are applied to the top and bottom select drivers. When these drivers receive the set strobe, the selection signals are supplied to top and bottom selection switches. The X and Y selection is accomplished by current steering circuits according to the coin¬ cident-current selection technique. Figure 4-150 is a simplified diagram of the selec¬ tion circuits. Each selection signal, generated as a result of the address from reg¬ ister S, effectively closes one top or bottom selection switch. Any one of 32 lines can be selected by closing one top and one bottom selection switch. The +13 volts and ground connections are interchanged, depending upon whether a read or a write oper¬ ation is being performed.

During the read operation, the X and Y selection signals are supplied to the selec¬ tion switches through the select drivers (figure 4-148). The read strobe enables the top selection switches and allows current to flow from the bottom selection switches through the core array to the top selection switches. The current flowing through the X and Y lines coincides at the addressed storage location in the core array. When this occurs, the 16 cores in the storage location are switched to a logic ZERO if they were not previously set. Those cores previously set remain at a logic ZERO. As a result, current is induced into the sense lines which thread those cores that switched to a logic ZERO. The current on the sense lines is detected by the sense amplifiers and applied to register G when the sense strobe is generated.

The selection switches remain set until the reset strobe is received on the reset windings. When the selection switches are reset, current is induced on the X and Y selection lines within the core. The write strobe enables the bottom selection switches and allows current to flow from the top selection switches through the core array to the bottom selection switches. Again the current flowing through the X and Y lines coincides at the addressed storage location in the core array. The cores in the ad¬ dressed location are switched to a logic ONE, provided they are not also receiving current on the inhibit lines. All cores receiving inhibit current remain in a logic ZERO. Inhibit current is governed by the content of register G. If an inhibit driver receives a bit containing a logic ONE, the driver is gated on by the inhibit strobe and inhibit current is supplied to a bit plane. There are 16 inhibit drivers, and each driver is connected to a bit plane. Thus, the content of register G determines which cores in a storage location are switched by the X and Y drive lines during the write operation.

4 -8.6. 1.5 Sense Amplifiers. There are 16 sense amplifiers in erasable memory. Each amplifier senses the contents of a bit location during the read operation. The bipolar sense signals are converted to single -polarity signals and forwarded to regis¬ ter G when the amplifiers are gated with the sense strobe. In addition, the word read out of fixed memory is also gated through the erasable memory amplifiers to register G.

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+I3V (WRITE) GND (READ)

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+ I3V (READ) GND (WRITE)

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Figure 4-150. X and Y Selection, Simplified Diagram

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APOLLO GUIDANCE AND NAVIGATION SYSTEM

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MANUAL

4-8. 6. 2 Erasable Memory Detailed Description. The functional presentation of the core array, timing circuit, address decoder, selection circuits, and the sense amplifiers in erasable memory are detailed in the following paragraphs.

4-8. 6. 2.1 Core Array. The core array (figure 4-151) contains 16 bit planes. Each bit plane consists of 1024 cores arranged in 32 columns and 32 rows. An individual bit is selected by the intersection of X selection lines (XT, XB) and Y selection lines (YT, YB) threading a core. The selection lines are threaded through the cores so that one core on each bit plane is selected by a given X - Y combination. Each core selected is in the same location in every bit plane at the intersection of the X and Y selection lines carrying current. The location of the line intersection is determined by addressing via the selection circuits. The 16 selected cores, one per bit plane, constitute a word storage location. The direction in which current flows through the lines determines whether data is being written into or read out of a selected core.

In addition to the X and Y lines, each core in a bit plane (figure 4-152) is threaded by an inhibit line and a sense line. Current through the inhibit line is in opposition to the X and Y selection currents and prevents all unselected cores in the bit plane from being switched since it cancels one-half the selection current. Current is induced into the sense line if the state of any core is changed from a ONE to a ZERO; no current is induced if the core is already in a ZERO state. The sense lines are connected to 16 amplifiers which amplify the current in a sense line and provide the power necessary to write ONE’s into register G of the central processor. It is in this manner that the contents of an erasable memory location are detected.

Before a storage location in erasable memory is written into, the location must be cleared. This is accomplished by applying reset signals to the selection switches. All the cores of the addressed location which are in the ONE state will change to the ZERO state; all cores in the ZERO state remain in that state. When the particular storage location is written into, current is sent through the X and Y selection lines as previously discussed but in the opposite direction. A current is fed also into the inhibit lines of all bit planes in which no ONE is to be written (i.e. , where a ZERO should remain in a particular core). At write time several different current conditions exist for the various cores. Whenever a core is intersected by only one selection line (X or Y), the core remains in its existing state. Whenever a core is intersected by one selection line (X or Y) and an inhibit line, the effects of both currents cancel, and the core remains in its existing condition. Whenever a core is intersected by two selection lines (one X line and one Y line) and an inhibit line, the net effect of all three currents is equal to the effect of a single select current (passing through a core of an addressed location which has been cleared), and the core remains in the ZERO state. Only if a core is intersected by two selection lines (one X line and one Y line) but not an inhibit line will a core change from the ZERO to the ONE state. It is in this manner that a 16-bit word is entered into erasable memory.

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APOLLO GUIDANCE AND NAVIGATION SYSTEM

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Figure 4-151.

Core Array

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APOLLO GUIDANCE AND NAVIGATION SYSTEM

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APOLLO GUIDANCE AND NAVIGATION SYSTEM

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MANUAL

4-8. 6.2.2 Erasable Memory Cycle Timing. Erasable memory cycle timing (figure 4-153) consists of several flip-flop circuits, which produce the timing signals for erasable memory. These timing signals (refer to figure 4-149) are produced in one memory cycle time (T01 through T12). Bits 11 and 12 (ST11 and ST12) from register S are logic ZERO'S when erasable memory is addressed. This condition, coincident with memory cycle signal (MC), produces a ferrite gating signal (FER), provided signal SCAD is a logic ZERO. A ONE in either bit position 11 or 12, or both, indicates an address in fixed memory. Signal SCAD is a logic ONE when a flip-flop register is addressed. The generation of FER allows the flip-flops to be set at the times indicated.

The set strobe (SETEK) is initiated when timing signals T04 and B2 are coincident and is terminated when signals T07, B2, and Q2 are coincident (figure 4-153). Signal SETEK conditions the core selection switches to be addressed. The flip-flop formed by gates 53314 and 53315 produces strobe signal SBE, which enables the sense amplifiers to supply data to register G. The flip-flop is set by signal T05 and B2 and reset by signals T06 and B2. Read strobes REX and REY enable data to be read out of erasable memory. These two strobes are generated simultaneously at time 5 and inhibited when signals T07 and Q2X are coincident. The flip-flops associated with signals SETEK, SBE, REX, and REY are also reset by signal GO JAM. Thus, data cannot be read out of erasable memory while signal GOJAM is present.

The inhibit strobe (ZID) gates the inhibit drivers when a ZERO is to be written into erasable memory. Signal ZID is generated by flip-flop gates 52303 and 52304 when signals TIP and Q2X are coincident. The flip-flop is reset at time 1. The reset strobes RSTKX and RSTKY are produced simultaneously when signals T 10 and B2 are coincident. These signals enable the reset drivers, thereby clearing the addressed memory location prior to writing in data. The reset strobe flip-flop, consisting of gates 52314 and 52315, is reset by signals T02, B2 and Q2. Write strobes WEX and WEY are generated from time 11 to time 1 by flip-flop gates 52308 and 52309. Signal T01 is inverted and supplied to fixed memory cycle timing. The flip-flops which produce the inhibit, reset, and write strobes are reset by signal TIMR. Signal TIMR is generated as the result of stop signals STPA and STPB, which occur at time 12. Timing signals P01 through P03, and P05 control the generation of TIMR to ensure the signal is not generated until after the completion of the strobes.

4-8. 6. 2. 3 Address Decoder. A storage location in erasable memory is addressed by X and Y coordinates. There are 32 X coordinates and 32 Y coordinates (figure 4-154). The X coordinate is controlled by signals XT0 through XT3 and XB0 through XB7; the Y coordinate is controlled by signals YT0 through YT3 and YB0 through YB7. Signals XT, XB, YT, and YB are generated as a function of bits ST01 through ST10 from register S (figure 4-155). The three lowest-order bits, ST01 through ST 03, produce signals XB0 through XB7 (see table 4-XIII); bits ST04 and ST05 produce XT0 through XT3 bits; bits ST06 through ST08 produce YB0 through YB7; and bits ST09 and ST10 produce XT0 through XT3.

4-320

APOLLO GUIDANCE AND NAVIGATION SYSTEM

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MANUAL

BPLSMV

Figure 4-153. Memory Cycle Timing - Erasable

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APOLLO GUIDANCE AND NAVIGATION SYSTEM

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MANUAL

Combinations of control signals XT, XB, YT, and YB, produced as a result of octal addresses 0000 through 1777, set the proper selection switches which are associated with each control pulse. Addresses 0000 through 0017 are reserved for the addressable flip-flop registers, 0020 through 0027 for special registers, 0034 through 0057 for the various counters, and 0060 through 1777 for general storage.

4-8. 6.2.4 Selection Circuits. As previoulsy stated, information is written into and read out of a storage location by means of core selection. This selection is performed by selection switches and associated driver circuits (figure 4-156). Since X and Y operations function the same, only one set of selection switches (X bottom and X top) and their associated drivers (X bottom, X top, X read, X write, and X reset) is discussed. Signal names and pin numbers for other circuits than those discussed may be found on figure 4-156.

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4-323

APOLLO GUIDANCE AND NAVIGATION SYSTEM

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MANUAL

Table 4-XIII. Register S Bit Assignments

Signal	Bit	Signal	Bit	Signal	Bit	Signal	Bit
10	9	8	7	6	5	4	3	2	1
YTO	0	0	YBO	0	0	0	XTO	0	0	XBO	0	0	0
YT1	0	1	YB1	0	0	1	XT1	0	1	XB1	0	0	1
YT2	1	0	YB2	0	1	0	XT 2	1	0	XB2	0	1	0
YT3	1	1	YB3	0	1	1	XT 3	1	1	XB3	0	1	1
			YB4	1	0	0				XB4	1	0	0
			YB5	1	0	1				XB5	1	0	1
			YB6	1	1	0				XB6	1	1	0
			YB7	1	1	1				XB7	1	1	1

The set strobe driver acts as a power switch for the bottom and top select drivers by suppling +13 vdc to the drivers. Signal SETEK forces transistor Q4 to conduct, which causes transistors Q5, Q6, and Q7 to conduct. When Q6 and Q7 conduct, B+ is supplied to the collectors of transistors Q13 and Q14, which causes both to conduct.

The read and write drivers operate in the same manner; therefore, only the write driver is discussed. Input signal WEX is inverted by transistor Q10. Diodes CR9 and CR10, emitter follower Qll, and resistor R17 stabilize transistor Q12 base current and the current through diodes CR11 and CR12. Transistor Q12 collector current rise time is controlled by inductor L2 and is independent of collector voltage.

The reset driver supplies a path for current through winding D of the selection switches to reset the cores. Signal RSTKX is inverted by transistor Q8. Diodes CR6, CR7, and CR8 maintain a constant voltage on the base of Q9, which provides a constant output current.

Each selection switch contains a ferrite selection core with four windings, two of which are connected to power transistors. Transistor Q1 of the X bottom selection switch and transistor Q17 of the X top selection switch form a path for read current. Transistors Q2 and Q18 form a path for write current. In order to generate a current on the X selection line, the selection switches and drivers must be energized.

Transistor Q1 in the bottom select driver conducts, via winding A of core Kl, only if control signal XBOE is present and signal SETEK is supplied to the set strobe driver. Current then flows through winding A and through Q14 which changes the state of Kl. When this occurs, a current is induced in winding B, which causes transistor Q1 of the bottom selection switch to conduct and transistor Q2 to be cut off. In a similar manner another control signal, XTOE, causes Q1 of the top select driver to conduct, and tran-

4-324

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SSIX

SS2X

SS3X

APOLLO 6UI DANCE AND NAVIGATION SYSTEM

ND-1021041

MANUAL

ST04

ST05

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Figure 4-155. Address Decoder (Sheet 1 of 2)

4-325/4-326

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ND-1021041

APOLLO GUIDANCE AND NAVIGATION

SYSTEM

MANUAL

SS6X

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Figure 4-155. Address Decoder (Sheet 2 of 2)

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APOLLO GUIDANCE AND NAVIGATION SYSTEM

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MANUAL

«e

		NPUT		OUTPUT
	SIGNAL NAME	FROM	TO	SIGNAL NAME	FROM	TO
40259 402SO 40261 40262	XTOE XTIE XT2E XT3E	AODRESS DECODER	87-07 07-03 87-04 87-08	40259A 40260A 40261 A 40262A	B7-06 B7-02 B7-0I B7-05	B8-24 B8-03 B8-07 B6-23

V BOTTOM SELECTION SIGNALS AND PIN

CKT	INPUT	OUTPUT
SIGNAL NAME	FROM	TO	SIGNAL NAME	FROM	TO
40251 40252 40253 40254 40255 40256 4025? 40258	X0OE SB 1 E X02E XB3E H04E X85E XS5E XB7E	ADDRESS DECODER	B7-24 87-15 B7-25 87-17 @7-21 87-11 87-20 07-12	40251 A 40252A 40253A 40254A 40255A 40256A 40257A 40258A	B7-23 87-16 87-22 B7-I4 B7-I8 87-10 87-19 87-09	@8-69 B8-47 BS-72 83-40 88-52 80-28 88-55 83-31

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40271 40272 40273 40274	Y TOE YTIE YT2E YT3E	ADDRESS DECODER	87-135 B7-I39 87-140 87-136	40271 A 40272A 40273A 40274A	87-138 87-142 87-141 87-137	88 8B s	-138 -142 -141 -127

CKT	OUTPUT	OUTPUT
SIGNAL NAME	FROM	TO	SIGNAL NAME	FROM	TO
40221 40222 40223 40224	IAY0F 2AYBF 3AYBF 4AYBF	88-125 88-139 88-140 88-122	CORE ARRAY	IBYBF 2BYBF 38YBF 4BYBF	88-121 08-131 88-132 88-120	CORE ARRAY

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SIGNAL NAME	FROM	TO	SIGNAL NAME	FROM	TO
40263 40264 40265 40266 40267 40268 40269 40270	YBOE YBIE Y82E YB3E YB4E Y85E Y86E Y87E	ADDRESS DECOOER	B7-I32 87-123 87-131 87-124 87-127 87-119 87-128 87-120	40263A 40264A 40265A 40266A 40267A 40268A 40269A 402 70A	87-133 87-126 87-134 87-125 B7-I30 B7-I22 87-129 87-121	88 88 88 88 88 B8 88 88	-117 -96 -120 -95 -100 -76 -103 -79

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SIGNAL NAME	FROM	TO
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40214	YAF02	B8-87
40215	YAF03	08-111
40216	YAF04	B8-86	W <J
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40218	YAF06	B0-8I
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Figure 4-156. Selection Switches and Drivers

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APOLLO GUIDANCE AND NAVIGATION SYSTEM

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MANUAL

sistor Q13 changes the state of K9. As K9 switches, transistor Q17 is forced to conduct and transistor Q18 is cut off. At the time that transistor Q1 and Q17 are conducting and signal REX is applied to the X read driver, read current flow from B+ to B- (+3V) through transistor Ql in the bottom selection switch, the core array, transistor Q17 in the top selection switch, and transistor Q13 in the read driver.

Generating a write current is similar to generating a read current. Signal RSTKX enables the reset driver, which allows current to flow through winding D of both selection switches. Current through winding D resets cores K1 and K9, which in turn induces current into both C windings causing transistors Q2 and Q18 to conduct and transistors Q1 and Q17 to cut off. At the same time signal WEX enables the write driver. A current path is provided from B+ to B- through transistor Q18, the core array, transistor Q2, and transistor Q12 in the write driver.

The inhibit line drivers prevent the setting of a core in erasable memory when a ZERO is to be written into a bit location. In order to address a storage location, 16 inhibit line drivers are required, one per bit plane. Each driver (figure 4-157) receives + 13 vdc signal (40017A) when inhibit strobe ZID occurs from memory cycle timing, and one bit (GEM01 through 16) from register G. During the write operation, ZID initiates a power switching action similar to that of the set strobe driver and B+ is applied to the collectors of transistors Q1 and Q2. If the input from register G is a logic ONE, Q1 conducts and inhibits Q2 and Q3. This prevents current from flowing through the inhibit line and the addressed core can be switched to the ONE state. When the input is a logic ZERO, the signal is inverted by Ql, which enables Q2 and Q3. When transistor Q3 is enabled, a path is provided for the inhibit current, which prevents the switching of the addressed core.

4-8. 6. 2. 5 Sense Amplifiers. Sixteen sense amplifiers (one per bit plane) are associated with erasable memory. Each sense amplifier (figure 4-158) accepts bipolar signals (SAF01 through 16 and SBF01 through 16) from the core array sense lines. When a core switches from a ONE state to a ZERO state, a current is induced in the sense line and applied to transformer Tl. The output of T1 is applied to a differential amplifier con¬ sisting of transistors Ql and Q2. Base bias voltage Vz is applied to the bases of Ql and Q2 via resistors R1 and R2. Transistor Q3 is constant-current source for the differential amplifier and establishes the dc operating point. Voltage Vx establishes the bias for transistor Q3. The output from the differential amplifier is OR'ed at the bases of a threshold detector consisting of Q5 and Q6. The collector of Q2 supplies the base input of Q5, and the collector of Ql supplies the base input of Q6. This produces a single-polarity output, even though the input waveform is bipolar. The threshold for Q5 and Q6 is set by voltage Vy, which is connected to the emitters of Q5 and Q6. Tran¬ sistors Q5 and Q6 cannot be switched on unless the base drive exceeds a predetermined level established by Vy. The sense amplifier outputs (SA01 through SA16) are fed through transistor Ql to register G by strobing Q4 with signal STBE from the strobe driver. Data from fixed memory (40410A through 40417A and 40420A through 40427 A) is fed also through Ql to register G.

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Voltages Vx, Vy, and VZt which are required for sense amplifier operation* are provided by a constant-voltage source. Base bias voltage Vz is maintained at a constant value by diodes CR1 and CR7 through CR10. Diodes CR2 through CR5 set the operating point for transistors Q3 and Q4. Zener diode CR6 compensates for any changes in B+ to maintain the values of Vx and Vy relatively constant.

The strobe driver (figure 4-159) receives erasable memory strobe signal SBE and fixed memory strobe signal SBF from their respective memory cycle timing circuits. The strobe signals are amplified and supplied to the appropriate sense amplifiers as signal STBE and STBF. These signals enable data to be transferred from the sense amplifiers to register G.

4-8. 6. 3 Fixed Memory Functional Description. Fixed memory (figure 4-160) consists of the fixed memory cycle timing circuits, bank register, selection logic, core ropes and drivers, and the sense amplifiers. Memory cycle timing generates the timing signals necessary for fixed memory operation. A location in fixed memory is ad¬ dressed according to the contents of register S in the central processor and the bank register (register BNK) in fixed memory. The selection logic converts the contents of registers BNK and S into the various signals necessary to select the addressed storage location. The three core ropes which are the storage medium for storing data in fixed memory are designated ropes R, S, and T. A rope consists of two modules, each of which contains four planes. Each plane in a module (figure 4-161) contains 128 cores arranged in a 4-by-32 matrix. The sense amplifiers detect the content of the addressed storage location and supply this data through the sense amplifiers in erasable memory to the central processor.

4-8. 6. 3.1 Magnetic Core. The characteristics of the magnetic cores used in fixed memory are similar to those of the ferrite cores used in erasable memory. However, the rope core differs from the ferrite core in that it is fabricated from 1/8 mil Mo- perm ribbon wound on a steel bobbin. Use of the Mo-perm ribbon allows the size of the fixed memory core to be large (core diameter is approximately 0.25 inch com¬ pared with 0.05 inch of the erasable memory core) without requiring large drive cur¬ rents, as would be the case if ferrite were used. The larger size is needed to accom¬ modate the number of wires required to thread the rope core (a maximum of 146 wires compared with 4 wires in the ferrite core).

4-8. 6. 3. 2 Fixed Memory Cycle Timing Circuits. Fixed memory cycle timing (figure 4-162) consists of timing control and timing flip-flops. The timing control regulates the generation of timing signals, used for fixed memory operation, by means of signal ROP. Signal ROP is generated when either bit 11 or bit 12 or both are logic ONE's and signal MC Is present. Signal ROP occurs for memory addresses above 1777. The timing flip-flops generate the timing signals (figure 4-162) necessary to sequence the operation of fixed memory subject to signals B2 and Q2 from the timer. The timing signals generated are RGENVX (conditions the set and reset circuits), IHENV (inhibit),

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APOLLO GUIDANCE AND NAVIGATION SYSTEM

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4-333/4-334

i

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APOLLO GUIDANCE AND NAVIGATION SYSTEM MANUAL

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APOLLO GUIDANCE AND NAVIGATION SYSTEM

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set 2 (set), SBF (enables sense amplifiers), and RSTRP (reset). Signal RGENV is used for enabling the bank selector gates. The generation of the set and inhibit signals is inhibited by signal GOJAM from the timer and the remaining timing signals are inhibited by signal TIMR from the erasable memory cycle timing circuits whenever a monitor stop or alarm condition exists.

4-8. 6. 3. 3 Bank Register. The bank register (figure 4-160) receives its contents on write lines 11 through 14 and 16 from the central processor. When the bank register is addressed (address 0015) and signal WSC12 is present, the flip-flop register is cleared by signal CBKG from the clear gates. The contents on the write lines are then entered into the flip-flop register by signal WBKG, via signal WSC234 to the write gates. The output from the bank register (R0 through R4, R0, Rl, and R2) is supplied to the selection logic where, along with other signals, it selects the proper rope and strand signals. The output from the register is supplied also to the central processor through the read gates, subject to signal RSC234.

4-8. 6. 3. 4 Selection Logic. The selection logic (figure 4-160) generates the rope, strand, set, and inhibit signals necessary to select an addressed storage location in fixed memory. The bank selector gates produce the following signals:

(1) One of six rope control signals (RPGl through RPG6)

(2) IL09A (used for set selection)

(3) IL10A and IL10A (used for strand selection)

The above signals are produced as a result of signals ST11 and ST12 from regis¬ ter S, and output signals of the bank register, subject to timing signal RGENV.

A rope is selected by enabling one of three rope return circuits with signals GATER, GATES, and GATET. These signals are produced by the rope selector, sub¬ ject to the rope control signals.

A sense strand is selected by gating signals GTRS through GTWS from the rope selector with strand gate signals SD00 through SD07 from the strand gates. The strand gate signals are generated by gating signals YTO through YT3 from erasable memory with IL10 and IL10A. This 6-by-8 combination selects 1 of 48 sense strands.

Set selection is accomplished by gating signals ST08 and ST08 with signal IL09A from the bank select gates. The gating actions produce one of four set signals, SET A through SET D, subject to timing signal SET 2.

Inhibit selection is divided into two parts. Bits 1 through 7 of register S and their complements determine which of the 14 inhibit lines is activated, and the remaining two lines are activated by gating bit 9 of register S with signal PARTY 9 from the parity logic in the central processor.

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MANUAL

f(CKT 40409)

(BPLSIW)

STBF *

NOTE

* TO ROPE MEMORY SENSE AMPLIFIER CIRCUITS (FIGURE 4-131) if* TO ERASABLE MEMORY SENSE AMPLIFIER CIRCUITS (FIGURE 4-120)

Figure 4-159. Strobe Driver

4-338

APOLLO GUIDANCE AND NAVIGATION SYSTEM

REGISTER

S

SEQUENCE

GENERATOR

ERASABLE

MEMORY

ND-1021041

MANUAL

RETURN

CIRCUITS

Figure 4-160. Fixed Memory, Functional Diagram

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MANUAL

PLANE A PLANE B PLANE C PLANE D

40436

B2

Q2

RGENVX

IHENV

SET 2

SBF

RSTRP

r

40437

Figure 4-162. Fixed Memory Cycle, Timing Diagram

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MANUAL

4-8. 6. 3. 5 Cores, Ropes, and Drivers. As previously stated there are three core ropes in fixed memory designated ropes R, S and T, and each rope (figure 4-163) consists of two modules.

There are 4 set drivers, 2 reset drivers, and 16 inhibit drivers. The set drivers are enabled subject to timing signals RGENVX. The reset drivers are enabled subject to timing signals RGENVX and RSTRP. The inhibit drivers are enabled subject to timing signal IHENV. The drive lines (4 set, 2 reset, and 16 inhibit) threading the three ropes are connected in parallel, but return to three separate rope return cir¬ cuits. Thus a particular rope is selected by enabling the appropriate rope return cir¬ cuit. This enabling occurs when one of three signals (GATER, GATES, or GATET) from the rope selector is received.

The sense lines threading or bypassing each core are grouped together into strands. A strand consists of 16 sense lines (one per bit), and there are 16 strands per rope for a total of 48 strands in fixed memory. However, only one strand select signal is present at a time. The strands are threaded through a rope such that eight strands thread or bypass all cores in a module (half a rope). Therefore, when any one strand select signal is present, one word (one of eight) of each core in a module is conditioned.

The fourteen inhibit lines, which thread or bypass all cores in a rope, inhibit 127 cores in each plane leaving eight cores (one per plane) available for selection. All cores are threaded by an additional inhibit signal (parity inhibit) or its complement, which is used for noise reduction in the sense lines.

Four set lines thread through each rope (each set line threads all cores in one plane of each module). By enabling one of the four set lines, two of the eight planes in a selected rope are enabled by the set line. The selected strand signal however, threads only one module. Thus, only one of the eight planes is actually selected by a set signal.

The selected word is detected and amplified by 16 sense amplifiers, which are en¬ abled by signal SBF. The reset signal (there are two reset signals, each threads 512 cores) resets the core switched during set time.

The above mentioned selection process occurs as follows:

(1) Rope select, selects 1 of the 3 core ropes R, S, and T when one of three rope return signals (GATER, GATES, or GATET) is received.

(2) Strand select, combination of one strand gate signal and one rope select sig¬ nal will condition 512 words in a rope module (one word per core).

(3) Inhibit, combination of fourteen signals which will inhibit 508 cores in a rope module leaving one core per plane to be selected.

(4) Set, one of four signals which will set one of the cores not inhibited previ¬ ously.

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MANUAL

SET A 1 THRU		1 I LOI THRU IL07, ILP	1 ROPE SELECT SIGNAL	1 STRAND GATE	IGNAL	STROBE(SBF)
SET D	RSTRP	| AND COMPLEMENTS	(GT_S)	(SDOO THROUGH	SD07)	—

SET

DRIVER

CIRCUIT

r

PLANE B	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
128 CORES	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

PLANE C 128 CORES

RESET

DRIVER

CIRCUIT

RESET

RETURN

CIRCUIT

p LEaDS r1 lf LEADS J7, LEADS | 32 LEADS ^32 LEADS | j^32 LEADS |

TO SENSE AMPS

TO SENSE AMPS

ROPE SELECT SIGNAL (GT_S)

TO SENSE AMPS

TO SENSE AMPS

TO SENSE AMPS

STRAND GATE SIGNAL (SDOO THROUGH SD07)

TO SENSE AMPS

L| -

TO SENSE AMPS

L| -

1

TO SENSE AMPS

STRAND

SIGNAL

STRAND

SIGNAL

STRAND

SIGNAL

STRAND

SIGNAL

STRAND

SIGNAL

STRAND

SIGNAL

STRAND

SIGNAL

STRAND

SIGNAL

PLANE D	i	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
128 CORES	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

r u i L	r 1 — 1 1 L	r 1 -j 1 L
SET		RESET		INHIBIT
RETURN		RETURN		RETURN
CIRCUITS		CIRCUIT		CIRCUITS

GATE-

(ROPE RETURN SELECT SIGNAL

Lp l;aos[j

TO SENSE AMPS

L' - [“*

T*

L |

32 LEADS

L

TO SENSE AMPS

TO SENSE AMPS

|~32 LEADS | ^

TO SENSE AMPS

I _ I

32 LEADS

r-

L | -

r “f

TO SENSE AMPS

TO SENSE AMPS

TO SENSE AMPS TO SENSE AMPS

PLANE A	1	1	1	1	1	1	1	1	1	l |	1	1	• 1	I	1	1	1	1	1	1
128 CORES	1	1	1	I	1	1		1	1	1 I	1	1	1 1	1			1			1
1 | | 1 1 1 1 1 I 1 | 1 1 II	I' 1 1 1 1 1
PLANE 8	1	1	1	1	1	1	1	1	1	1 |	1	1	I 1	1	1	1	1	1	1	1
128 CORES	1	1	1	1	1	1	1	1	1	1 1	1	1	j 1	1	1	1	1	1	1	1
1 | | 1 | 1 1 | 1 1 1 1 | II	1 1 II 1 1 1
PLANE C	1	1	l	1	1	1	1	1	1	1 1	1	1	1 1	1	1	1	1	1	1	1
128 CORES	1	1	1	1	1	1	1	1	1	1 1	1	1		1		1	1			1
1 1 | 1 | f | 1 I | 1 1 1 1 11	1 1 II 1 i 1
PLANE D	1	1	1	1	1	1	1	1	1	1 1	1	1	| 1	1	1	1	1	1	1	1
128 CORES	I	1	1	1	1	1			1	1 '	1	1	1	1		l	1		1	1

r

INHIBIT

DRIVER

CIRCUIT

1 r

STRAND

CIRCUITS

r

STRAND

SIGNAL

SENSE LINES

n r

STRAND

SIGNAL

STRAND

SIGNAL

SENSE LINES

j SENSE LINES I

STRAND

SIGNAL

SENSE LINES

n r

STRAND

SIGNAL

SENSE LINES

n r

STRAND

SIGNAL

SENSE LINES

1 r

■j

SENSE LINES

STRAND

SIGNAL

n r

SENSE LINES

STRAND

SIGNAL

n

o±\

SENSE

oUT_| AMPLIFIERS

RESET		1
DRIVER	1	1	STRAND	SELECT	CIRCUITS
CIRCUIT	1 1	1 1

1	1 1	1 - 1		i i	i i	[~ SENSE	LINES ' 1	j” SENSE	LINES j	^ SENSE LINES ' I 1	1"” SENSE LINES j	j” SENSE	1 NE S 1 1	SENSE LINES 1	1 1	r i	SENSE LINES j	r l	SENSE LINES j
PLANE A | I28CORES 1	1 1	1 1	i 1	i i	i 1	1 1	1 1	1 1	1 1	1 1 1 1	1 1 1 1	i	1 1	1 1	1 1	i i	1 1	i 1	1 1

<4^

o^\

07H

_ I

Figure 4-163. Rope Organization

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MANUAL

(5) Sense strobe, enabling signal from timing circuits used for the detection of the selected word.

(6) Reset, signal that resets the core, selected during set time, to its normal state.

4-8. 6. 3. 6 Sense Amplifiers. As in erasable memory, there are 16 sense amplifiers in fixed memory. Each amplifier amplifies the data on the selected sense line and for¬ wards the data to erasable memory, when enabled by timing signal SBF.

4-8. 6.4 Fixed Memory Detailed Description. Fixed memory is a nondestructive, random-access storage device. Data is wired into fixed memory; therefore, it cannot be altered electrically. Fixed memory consists of core ropes, memory cycle timing, bank register, selection logic, driver and return circuits, and sense amplifiers.

4-8. 6. 4.1 Core Ropes. A core rope is a storage device in which information is stored by wiring the cores in a unique manner. There are three core ropes in fixed memory; R, S, and T (modules B28 and B29, B21 and B22, B23 and B24 respectively). Each core rope module (figure 4-164) contains four 128-core planes for a total of 512 cores in a rope module.

Each core in a rope module stores eight 16-bit words. A total storage capacity of 24,576 sixteen-bit words is provided by fixed memory. A core is threaded or bypassed by set, reset, inhibit, and sense lines (one per bit). The effect of currents passing through a core via the set, reset, and inhibit lines is additive. The currents in the set lines and the inhibit lines are of opposite polarity; therefore, the set current is cancelled by the inhibit current when the currents are time-coincident. Thus, a core changes state at set time if none of the inhibit lines threading the core is carrying current. When a core changes state, current is induced into all the sense lines threading the core. The sense lines bypassing the core receive no curent. In this manner the sense lines associated with each core receive the same words each time the core is set. A core is reset when current flows through the reset line.

Inhibit signals IL01 through IL07 and their complements are sufficient to select one core in each plane. A core is selected by inhibiting all but one core in each plane. Inhibit signals ILP and ILP ensure that all but the selected core are inhibited by at least two signals and thus the noise in the sense lines is reduced. Four set lines thread each core rope, and each set line threads all cores of one plane in each rope module. Only one set signal is present at set time, and that signal is selected by address. The sense lines threading or bypassing each core are grouped into strands. A strand con¬ sists of the sense lines necessary to detect one 16-bit word. There are 8 strands per rope module, for a total of 48 strands in fixed memory. With the application of a rope select signal (one of six) and a strand select signal (one of eight), a particular strand (one of forty eight) is selected. The matched diodes shown on the sense lines (figure 4-164) are used for bipolar operation.

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MANUAL

4-8. 6.4. 2 Fixed Memory Cycle Timing. Fixed memory cycle timing (figure 4-165) con¬ sists of several flip-flops and gates on modules A33 and A34 which produce the timing signals necessary to perform the set, reset, inhibit, and sensing functions in fixed memory. As in erasable memory all the timing pulses are generated in one memory cycle time (11.97 microsecond). A logic ONE in either bit position 11 or 12, or both, indicates that fixed memory is addressed. This condition, coincident with signal MC, produces rope condition signal ROP. Signal ROP must be present to generate the fixed memory timing signals.

The waveforms for fixed memory cycle timing are illustrated in figure 4-162. At time 2, FF52325-52326 is set by signal GTON and generates output RGENV and RGENVX. These outputs are present until time 1 of the next memory cycle. Signal RGENV enables the bank selector gates in the selection logic. Signal RGENVX is the conditioning signal for the set and reset driver circuits. Also at time 2 as a function of GTON, inhibit signal IHENV is generated. This signal is present until time 8 and enables the inhibit drivers in the driver and return circuits to allow inhibit current to flow through the selected inhibit line.

At time 4 (coincident with Q2X from the timer) signal SET 2 is generated (FF53328- 53329) and enables the set selector circuits. At time 6, strobe signal SBF (approximately 1 microsecond in duration) is generated and enables the sense amplifiers. At time 8 the inhibit signal IHENV and the SET 2 signal are reset. Coincident with this action, reset signal RSTRP is generated which enables the reset drivers and allows current to flow in the reset lines.

4- 8. 6. 4. 3 Bank Register. A location in fixed memory is addressed according to the contents of register S and the bank register (BNK). Register BNK (figure 4-166) is a

5- bit addressable flip-flop register. Clear (CBKG), write (WBKG), and read (RBKG) pulses are generated when signals XT1 and XB5 (address 0015) are coincident with control pulses WSC12, WSC234, and RSC234, respectively. Signal CBKG clears register BNK before bits 16 and 14 through 11 enter the register on write lines WL16 and WL14 through WL11, subject to signal WBKG. If the data on the write lines is a ZERO, the associated bit position in register BNK remains cleared. The contents of the register are supplied to the bank selector (subject to signal RBKG) as signals R0 through R4, R0, Rl, and R2 and to the central processor as signals RWL16 and RWL14 through RWL11.

4-8. 6. 4. 4 Selection Logic. The selection logic converts the contents of registers S and BNK into the various signals necessary to select the addressed storage location. Fixed memory has the capability of addressing 32 banks; however, there are only 24 banks physically available for use. The first two banks (table 4-XTV) are designated fixed-fixed (FF) memory and the remaining 22 banks are designated fixed-switchable (FS) memory. Whenever a location in FF memory is addressed, a ONE in either bit position 11 or 12, is present in register S. A location in FS memory is addressed when both bit positions 11 and 12 contain a ONE. Locations in FF memory and bank 03 of FS memory are addressed by the content of bit positions 12 through 1 of register S.

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MANUAL

NOTES;

THREADS CORES

BYPASSES CORES

THREADS OH BYPASSES CORES

I- STRAND CSD„_) - GATING SIGNAL FOR THE STRAND SELECT CIRCUITS. THE COMBINATION OFA STRAND SIGNAL.SONE OFEIGHT) AND A ROPE SELECT SIGNAL. ®T„S CONE OF SIX), PRODUCES ONE SDR__ SIGNAL.

2. SENSE LINES -THREADS OR BYPASSES 512 CORES CONSTRUCTING ONE WORD (56BITS) IN EACH CORE. ONLY ONE OF THE EIGHT GROUPS OF SENSE LINES IS ACTIVE AT A TIME. ALL SENSE LINES ARE TIED TO SIXTEEN SENSE AMPLIFIERS SHOWN.

S. INHIBIT -128 C2?5 COMBINATIONS OF SIGNALS FOR ADDRESSING WHICH THREAD OR BYPASS 512 CORES INHIBITING 127 CORES IN EACH PLANE !5©8 TOTAL?. PARITY SIGNALS ( ILP AND ILP) ENSURES AT LEAST TWO INHIBITS PER CORE FOR THE 128 COMBINATIONS.

4. SET - THREADS 128 CORES SWITCHING THE CORE THAT WAS NOT INHIBITED ONLY ONE SET SIGNAL IS PRESENT AT A TIME.

5. STROBE- GATES OUT THE WORD CIS BITS} THAT WAS SWITCHED DURING SET TIME.

6. RESET - THREADS 512 CORES RESETTING THE CORE SWITCHED DURING SET TIME.

7 REFER TO NASA DRAWINGS IOG6I44 , AND 1006147 FOR IDENTIFICATION OF COMPONENTS.

©■ SITS I THROUGH 16 ARE SENT TO THE ERASABLE MEMORY SENSE AMPLIFIERS.

SET A SET B SET C SET D

SET DRIVER CIRCUITS

GATE™

(ROPE RETURN SELECT SIGNAL)

ILOI ILOI IL02 IL02 IL03 IL03 IL04 IL04 IL05 ILQ5 IL06 ILOS IL07 IL07 ILP

SD02

STRAND

SELECT CIRCUITS

- f-

Figure 4-164. Rope Module Organization

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MANUAL

Table 4-XIV. Addressing

			Octal Address	Pseudo Address	Contents of BNK*	Contents of S*
			Real	Pseudo	(Decimal)	15	14	13	12	11	12	11	10	9	8	7	6	5	4	3	2	1
		FF	BANK 01	2	100	3777	Same	1024	2047	X	X	X	X	X	0	1	X	X	X	X	X	X	X	X	X	X
		02	4	100	5777	Same	2048	3071	X	X	X	X	X	1	0	X	X	X	X	X	X	X	X	X	X
			03	6	300	7777	6000	7777	3072	4095	0	0	0	X	X	1	1	X	X	X	X	X	X	X	X	X	X
			04	6000	7777	10000	11777	4096	5119	0	0	1	0	0	1	1	X	X	X	X	X	X	X	X	X	X
	Fi		05	61	>00	7777	12000	13777	5120	6143	0	0	1	0	1	1	1	X	X	X	X	X	X	X	X	X	X
			06	“3	o o	7777	14000	15777	6144	7167	0	0	1	1	0	1	1	X	X	X	X	X	X	X	X	X	X
			07		)00	7777	16000	17777	7168	8191	0	0	1	1	1	1	1	X	X	X	X	X	X	X	X	X	X
			10		00	7777	20000	21777	8192	9215	0	1	0	0	0	1	1	X	X	X	X	X	X	X	X	X	X
			11		00	7777	22000	23777	9216	10239	0	1	0	0	1	1	1	X	X	X	X	X	X	X	X	X	X
			12		[oo	7777	24000	25777	10240	11263	0	1	0	1	0	1	1	X	X	X	X	X	X	X	X	X	X
			13	6000	7777	26000	27777	11264	12287	0	1	0	1	1	1	1	X	X	X	X	X	X	X	X	X	X
			14	6000	7777	30000	31777	12288	13311	0	1	1	0	0	1	1	X	X	X	X	X	X	X	X	X	X
F	f2		21	6f>00	7777	42000	43777	17408	18431	1	0	0	0	1	1	1	X	X	X	X	X	X	X	X	X	X
			22	6000	7777	44000	45777	18432	19455	1	0	0	1	0	1	1	X	X	X	X	X	X	X	X	X	X
			23	6000	7777	46000	47777	19456	20479	1	0	0	1	1	1	1	X	X	X	X	X	X	X	X	X	X
			24	6000	7777	50000	51777	20480	21503	1	0	1	0	0	1	1	X	X	X	X	X	X	X	X	X	X
			25	6000	7777	52000	53777	21504	22527	1	0	1	0	1	1	1	X	X	X	X	X	X	X	X	X	X
			26	6000	7777	54000	55777	22528	23551	1	0	1	1	0	1	1	X	X	X	X	X	X	X	X	X	X
			27	6000	7777	56000	57777	23552	24575	1	0	1	1	1	1	1	X	X	X	X	X	X	X	X	X	X
			30	6	ioo	7777	60000	61777	24576	25599	1	1	0	0	0	1	1	X	X	X	X	X	X	X	X	X	X
	F3		31	6<j)00	7777	62000	63777	25600	26623	1	1	0	0	1	1	1	X	X	X	X	X	X	X	X	X	X
			32	6000	7777	64000	65777	26624	27647	1	1	0	1	0	1	1	X	X	X	X	X	X	X	X	X	X
			33	6000	7777	66000	67777	27648	29671	1	1	0	1	1	1	1	X	X	X	X	X	X	X	X	X	X
			34	6000	7777	70000	71777	29672	30695	1	1	1	0	0	1	1	X	X	X	X	X	X	X	X	X	X
					•		*X means 0 or 1

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APOILO GUIDANCE AND NAVIGATION SYSTEM

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MANUAL

Figure 4-165.

j 52331^-

J

SBF

40440

Memory Cycle Timing, Fixed

4-351/4-352

APOLLO GUIDANCE AND NAVIGATION SYSTEM

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MANUAL

MWBKG

WBKG

CBKG

RBKG

Figure 4-166. Bank Register

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APOLLO GUIDANCE AND NAVIGATION SYSTEM

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MANUAL

The remaining locations in FS memory are addressed by the content of both registers BNK and S. The content of bit positions R4 through RO of register BNK determines which bank (octal 04 through 34 with some exceptions) in FS memory is being addressed and the content of bit positions 10 through 1 of register S determines which location within the bank is being addressed.

Table 4-XV lists all the pseudo octal addresses for fixed memory. Although the addresses are pseudo to computer operation they are real for manual addressing via the DSKY's. Included in the table are the sets, strands, and banks associated with each of the locations. The inhibit combinations are too numerous for inclusion in the table.

_ The bank selector gates (figure 4-167) sense the state of signals RO through R4, RO, Rl, and R2 of register BNK and signals ST11 and ST12 from register S. This sensing operations results in the generation of one of six rope control signals (RPG1 through RPG6). The bank selector gates also generate set enabling signal IL09A and strand enabling signals IL10A and IL10A, as a result of the inputs from register BNK and S. The above signals select one of 24 banks in fixed memory subject to timing signal RGENV. Each bank consists of 1024 word locations. Table 4-XVI illustrates the relation¬ ship between the inputs and outputs of the bank selector gates and the associated bank.

The generation of an RPG signal is inhibited if signal MYCLMP is a logic ONE. Signal MYCLMP is a logic ONE only when the dc voltages supplied to memory are not within tolerance. If input signals RO through R4, RO, Rl and R2 do not represent a valid address, signal BALI (bank alarm one) or BAL2 is produced. These two signals are inverted and supplied to the CTS as signal MBAL.

The set selector (figure 4-168) gates signals ST08 and ST08 from register S with signal IL09A from the bank selector gates. By combining these inputs, one of four set signals (SET A, SET B, SET C, or SET D) will be generated subject to timing signal SET 2. The selected set signal is supplied to the set lines through driver circuits.

The seven low-order bits (ST07 through ST01) of register S and their complements are inverted by the inhibit gates (figure 4-169) and are applied to the inhibit lines through driver circuits. Signal ST09 of register S is gated by signal PARTY 9 from the parity tree in the parity gates (figure 4-169) to produce the parity inhibit signal (ILP) and its complement. The parity inhibit lines thread the cores, through driver circuits, to reduce noise in the sense lines. The PARTY 9 signal represents an even number of ONE’S in bits 9 through 1 of the address sent to the parity block.

The strand gates (figure 4-170) receive signals ST09, ST10 and their complements from register S and signals IL10 and IL10A from the bank selector gates. Combinations of these signals will produce one of eight strand gate signals designated SD00 through SD07. Table 4-XVII illustrates the manner in which the input signals are combined to produce the strand gate signals.

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APOLLO GUIDANCE AND NAVIGATION SYSTEM

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MANUAL

Table 4-XV. Bank Addressing

Pseudo		Rope R	Pseudo		Rope S
Octal Address	Set	Strand	Bank	Octal Address	Set	Strand	Bank
02000-02177		C	00	01	12000-12177		C	08	05
02200-02377		D	00	01	12200-12377		D	08	05
02400-02577		C	01	01	12400-12577		C	09	05
02600-02700	A	D	01	01	12600-12777	>* A	D	09	05
03000-03177	^A	C	02	01	13000-13177	Aa	C	10	05
03200-03377		D	02	01	13200-13377		D	10	05
03400-03577		C	03	01	13400-13577		C	11	05
03600-03777^		D	03	01	13600- 13777J		D	11	05
04000-04177*'		A	04	02	14000- 14 177^		A	12	06
04200-04377		B	04	02	14200-14377		B	12	06
04400-04577		A	05	02	14400-14577		A	13	06
04600-04777		B	05	02	14600-14777		B	13	06
05000-05177		A	06	02	15000-15177		A	14	06
05200-05377		B	06	02	15200-15377		B	14	06
05400-05577		A	07	02	15400-15577		A	15	06
05600-05777		B	07	02	15600-15777	“ A	B	15	06
	\ A
06000-06177		C	04	03	16000-16177		C	12	07
06200-06377		D	04	03	16200-16377		D	12	07
06400-06577		C	05	03	16400-16577		C	13	07
06600-06777		D	05	03	16600-16777		D	13	07
07000-07177		C	06	03	17000-17177		C	14	07
07200-07377		D	06	03	17200-17377		D	14	07
07400-07577		C	07	03	17400-17577		C	15	07
07600-07777 ->		D	07	03	17600-17777^		D	15	07
10000-10177*^		A	00	04	20000-20 177^		A	08	10
10200-10377		B	00	04	20200-20377		B	08	10
10400-10577		A	01	04	20400-20577		A	09	10
10600-10777	l A	B	01	04	20600-20677	rA	B	09	10
11000-11177	Z_A	A	02	04	21000-21177	A	10	10
11200-11377		B	02	04	21200-21377		B	10	10
11400-11577		A	03	04	21400-21577		A	11	10
11600-11777		B	03	04	21600-21777^		B	11	10
/\B28,	Ab29>	/^\B21, and	A	B22

(Sheet 1 of 3)

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Table 4-XV. Bank Addressing (cont)

			Rope T					Rope R
Pseudo					Pseudo
Octal Address	Set	Strand	Bank	Octal Address	Set	Strand	Bank
22000-22177 ^		C	16	11	42000-42177		C	24	21
22200-22377		D	16	11	42200-42377		D	24	21
22400-22577		C	17	11	42400-42577	V 0	C	25	21
22600-22777	A	D	17	11	42600-42777	D	25	21
23000-23177	C	18	11	43000-43177	C	26	21
23200-23377		D	18	11	43200-43377		D	26	21
23400-23577		C	19	11	43400-43577		C	27	21
23600-23777 J		D	19	11	43600-43777^		D	27	21
24000-24177^		A	20	12	44000-44177*'		A	28	22
24200-24377		B	20	12	44200-44377		B	28	22
24400-24577		A	21	12	44400-44577		A	29	22
24600-24777		B	21	12	44600-44777		B	29	22
25000-25177		A	22	12	45000-45177		A	30	22
25200-25377		B	22	12	45200-45377		B	30	22
25400-25577		A	23	12	45400-45577		A	31	22
25600-25777	'A	B	23	12	45600-45777	► A	B	31	22
26000-26177	C	20	13	46000-46177	C	28	23
26200-26377		D	20	13	46200-46377		D	28	23
26400-26577		C	21	13	46400-46577		C	29	23
26600-26777		D	21	13	46600-46777		D	29	23
27000-27177		C	22	13	47000-47177		C	30	23
27200-27377		D	22	13	47200-47377		D	30	23
27400-27577		C	23	13	47400-47577		C	31	23
27600-27777 J		D	23	13	47600-47777		D	31	23
30000-30177**		A	16	14	50000-50177*'		A	24	24
30200-30377		B	16	14	50200-50377		B	24	24
30400-30577	►A	A	17	14	50400-50577	‘A	A	25	24
30600-30777	B	17	14	50600-50777	B	25	24
31000-31177	A	18	14	51000-51177	A	26	24
31200-31377		B	18	14	51200-51377		B	26	24
31400-31577		A	19	14	51400-51577		A	27	24
31600-31777		B	19	14	51600-51777j		B	27	24
A B28-		A	B29,	^^B23, and B24

(Sheet 2 of 3)

4-357

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Table 4-XV. Bank Addressing (cont)

			Rope S						Rope T
Pseudo
				r'seuao
Octal Address	Set	Strand	Bank	Octal Address	Set	Strand	Bank
52000-52177			C	32	25	62000-62177			C	40	31
52200-52377			D	32	25	62200-62377			D	40	31
52400-52577			C	33	25	62400-62577			C	41	31
52600-52777		A	D	33	25	62600-62777		A	D	41	31
53000-53177		C	34	25	63000-63177		C	42	31
53200-53377			D	34	25	63200-63377			D	42	31
53400-53577			C	35	25	63400-63577			C	43	31
53600-53777	••		D	35	25	63600-63777			D	43	31
54000-54177	>		A	36	26	64000-64177			A	44	32
54200-54377			B	36	26	64200-64377			B	44	32
54000-54577			A	37	26	64400-64577			A	45	32
54600-54777			B	37	26	64600-64777			B	45	32
55000-55177			A	38	26	65000-65177			A	46	32
55200-55377			B	38	26	65200-65377			B	46	32
55400-55577			A	39	26	65400-65577			A	47	32
55600-55777		A	B	39	26	65600-65777		- A	B	47	32
56000-56177			C	36	27	66000-66177		C	44	33
56200-56377			D	36	27	66200-66377			D	44	33
56400-56577			C	37	27	66400-66577			C	45	33
56600-56777			D	37	27	66600-66777			D	45	33
57000-57177			C	38	27	67000-67177			C	46	33
57200-57377			D	38	27	67200-67377			D	46	33
57400-57577			C	39	27	67400-67577			C	47	33
57600-57777	>		D	39	27	67600-67777			D	47	33
60000-60177			A	32	30	70000-70177	■*		A	40	34
60200-60377			B	32	30	70200-70377			B	40	34
60400-60577			A	33	30	70400-70577			A	41	34
60600-60777 61000-61177		A	B A	33 34	30 30	70600-70777 71000-71177		A	B A	41 42	34 34
61200-61377			B	34	30	71200-71377			B	42	34
61400-61577			A	35	30	71400-71577			A	43	34
61600-61777	-S		B	35	30	71600-71777			B	43	34
/\B21,		/\B22-	A	B23, and		A	B24

(Sheet 3 of 3)

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r

Figure 4-167. Bank Selector Gates

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Table 4-XVI. Selector Gates - Inputs and Outputs

Register BNK	Register S	Set Enable Signal	Strand Enable Signal	Rope Control Signal	Bank
Input Bit
16	14	13	12	11
Output Signal*	Bit
RO	R1	R2	R3	R4	12	11	IL09A	IL10A
X	X	X	X	X	0	1	1	0	RPG1	01
X	X	X	X	X	1	0	0	1	RPG1	02
0	0	0	X	X	1	1	1	1	RPG1	03
0	0	1	0	0	1	1	0	0	RPG1	04
0	0	1	0	1	1	1	1	0	RPG2	05
0	0	1	1	0	1	1	0	1	RPG2	06
0	0	1	1	1	1	1	1	1	RPG2	07
0	1	0	0	0	1	1	0	0	RPG2	10
0	1	0	0	1	1	1	1	0	RPG3	11
0	1	0	1	0	1	1	0	1	RPG3	12
0	1	0	1	1	1	1	1	1	RPG3	13
0	1	1	0	0	1	1	0	0	RPG3	14
1	0	0	0	1	1	1	1	0	RPG4	21
1	0	0	1	0	1	1	0	1	RPG4	22
1	0	0	1	1	1	1	1	1	RPG4	23
1	0	1	0	0	1	1	0	0	RPG4	24
1	0	1	0	1	1	1	1	0	RPC. 5	25
1	0	1	1	0	1	1	0	1	RPG5	26
1	0	1	1	1	1	1	1	1	RPG5	27
1	1	0	0	0	1	l	0	0	RPG5	30
1	1	0	0	1	1	1	1	0	RPG6	31
1	1	0	1	0	1	1	0	1	RPG6	32
1	1	0	1	1	1	1	1	1	RPG6	33
1	1	1	0	0	1	1	0	0	RPG6	34

* x means 0 or 1

1

Figure 4-168. Set Selector Gates

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Table 4-XVII. Strand Gate Input and Output Signals

ST 10	ST09	IL10	SD
0	0	0	00
0	1	0	01
1	0	0	02
1	1	0	03
0	0	1	04
0	1	1	05
1	0	1	06
1	1	1	07

Since there are a total of 48 sense strands in fixed memory and 8 strands thread each rope module, a selection system is required to select the proper rope module and strand to read out data. This selection process is performed by the rope and strand selectors (figure 4-171). There are three identical rope selector circuits, and each circuit receives two RPG signals. However, only one signal is present at a time. In addition, there are eight strand selector circuits, each consisting of six gates. Each strand selector gate receives one of eight SD signals from the strand gates and one of six GTS signals from the rope selectors. This 6-by-8 combination selects the proper sense strand from among 48 possibilities. For simpliciation only one rope selector circuit (40501) and one strand selector circuit (40401) are discussed.

Assuming RPG1 (circuit 40501) to be a logic ONE, transistors Q1 and Q3 conduct, which results in signal GTRS (+13 vdc) being applied to CR1 in the eight strand selectors. In addition, diode CR1 in the rope selector is forward-biased, which enables the rope R return circuits with signal GATER. Thus, one rope return circuit is enabled, and eight gates (one per strand selector) are conditioned to be enabled. The application of a strand gate signal determines which of the eight gates is enabled. Assuming signal SD00 (circuit 40401) to be a logic ONE, transistors Q1 and Q2 conduct and sense strand SDR00 is selected. Table 4-XVIII illustrates the manner in which the 48 strand-select signals are produced as a result of combining the RPG and SD signals.

4-362

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_)

Figure 4-169. Inhibit Gates

4-363

APOLLO GUIDANCE AND NAVIGATION SYSTEM

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r

ILIOA

SDOO

Figure 4-170. Strand Gates

4-364

ND-1021041

MANUAL

Figure 4-171. Rope and Strand Selectors

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4-8. 6. 4. 5 Driver and Return Circuits. The set, reset, and inhibit lines threading or by¬ passing the three ropes are connected in parallel, but return to three separate rope return circuits (figure 4-160). Each line is driven by a separate driver circuit, and all lines which are common to a particular rope are treutnred to an associated circuit. There are 16 inhibit drivers, 4 set drivers, and 2 reset drivers.

The 16 inhibit drivers (figure 4-172) are enabled subject to signals IL01 through IL07 and their complements, and signal 40331 A (+13 vdc). Signal 40331A (circuit 40331) is generated subject to timing signal IHENV. Input signal IHENV turns on transistor Q15 which in turn will cause transistor Q16 to conduct and supply +13 vdc to the base of emitter follower Q17. The output of Q17 (40331 A) is supplied to all sixteen inhibit drivers. For simplication only one inhibit driver (circuit 40311) and one inhibit return (circuit 40353) are discussed.

Assuming signal IL01 (circuit 40311) to be a logic ZERO and signal 40331A to be present, transistor Q1 is cut off by signal IL01 and transistor Q2 is turned on by signal 40331 A. Simultaneously, signal GATET (circuit 40353) is a logic ZERO, transistor Q18 is turned on, which will then turn on emitter follower transistors Q19 and Q20 and supply + 13 vdc to diodes CR29 through CR36. Thus, the above operation provides a current path from +13 vdc (B+) through transistor Q19, diode CR29, core rope T, transistor Q2, resistor R4, and inductor LI to +3 vdc (B-).

The 4 set drivers (figure 4-173) are enabled subject to signals SET A, SET B, SET C, and SET D and signal 40332 A (+13 vdc) . Signal 40332A (circuit 40332) is generated subject to timing signal RGENVX. The operation of circuit 40332 is identical to circuit 40331 (inhibit) previously discussed. The output of Q17 (40332 A) is supplied to all four set drivers. For simplification only set driver (circuit 40361) and one set return (circuit 40351) are discussed.

Assuming signal SET A (circuit 40361) to be a logic ZERO and signal 40332A to be present, transistor Q3 is cut off by signal SET A and emitter follower transistor Q4 is turned on by signal 40332A. Transistor Q4 then turns on transistors Q5 and Q6 which connect signal XSETAD to the three core ropes and to three of the six return circuits. Signal XSETAD is connected to the return circuits for reduction of noise on the set lines. Simultaneously, signal GATER (circuit 40351) is a logic ZERO and transistor Q7 is turned on which will then turn on emitter follower transistor Q10 and supply +13 vdc to diodes CR16 and CR17. This operation provides a current path from + 13 vdc (B+) through transistors Q7 and Q10, diode CR16, core rope R, transistors Q5 and Q6, resistors R10 and Rll and inductors L2 and L3 to +3 vdc (B-).

The two reset drivers (figure 4-174) are enabled by timing signal RSTRP. The operation of the reset circuits and the set circuits is similar. Reset circuits 40332, 40367, and 40352 function the same as set circuits 40332, 40361, and 40351, respectively. However a difference exists in current path operation. When signal RSTRP is received and signal 40332A is present both circuits 40367 and 40368 are activated. This connects XRST1N and XRST2N to two separate rope return circuits. If signal GATES (circuits 40352 and 40355) is a logic ZERO, it will provide two current paths for reset operation.

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Table 4-XVin. Rope and Strand Selection Signals

Rope Control	Rope Return	Strand Gate	Sense Strand
RPG1	GATER	SDOO	SDROO
		through	through
		SD07	SDR 07
RPG2	GATES	SDOO	SDR 08
		through	through
		SD07	SDR 15
RPG3	GATET	SDOO	SDR16
		through	through
		SD07	SDR23
RPG4	GATER	SDOO	SDR24
		through	through
		SD07	SDR31
RPG5	GATES	SDOO	SDR32
		through	through
		SD07	SDR39
RPG6	GATET	SDOO	SDR40
		through	through
		SD07	SDR47

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» SELECTED m ELEC7RLC&L TEST

J 40447

Figure 4-172. Fixed Memory Inhibit Drivers and Return Circuits

4-369/4-370

I

+ 13V (BPLMZI)

[ROPE DRIVER (CKT A36	403325
i	R3I
1 680	2K
1 1 vw | R29
a98 . ^015		j 016
1 l vhfe. /

+ I3V (BPLIZl)

* SELECTED BY ELECTRICAL TEST

r_

i

I 3S

(CKT 40362)

( CKT 40363)

(CKT 40364)

25 XSETAD

_ I

B33

APOLLO GUIDANCE AND NAVIGATION SYSTEM

ND-1021041

MANUAL

[core rope r

-r

r

f8

■488

! B29

L

[core rope s

75

■¥ r -r

-j88

[b22_

[core rope t'

r- i82	RBSET	A*
V i77	RCSET	V
? ASL.	RDSET	it

1 76 SETARN

182 SETBRN

177 SETCRN

187 SETDRN

|B28_ J _ j

i

A76	SASET	r~ -675
A82	S8SET	i _ A81
A77	SCSET	T l70
? I07	SDSET	I88

1 76 SETASN

1 82 SETBSN

|77 SETCSN

,87 SETDSN

Lr

B2I

ii

A81	I76	TASET
? A82	TBSET	T A81
Y A78	? AIL-	TCSET	T A78
lee ? 1 B24	T A ®I_	TDSET	T .8S
Y J		T LB23

176 SETATN

182 SETBTN

1 77 SETCTN

|87 SETDTN

(CKT 40354)

[B33_

(CKT 40352)

i B32

-f

T

l_B3_3_

(CKT 40355)

(CKT 40353)

l_B32

-r

I AO

l_B33

(CKT 40356)

56(J) + I3V (BPLMYI )

8I(Jh< - GATER

73<j) + l3V(8PLMY3)

7l£- -

70

66(}h« - GATES

721 _ XSET8D

%

- GATES

72j^ XSETDD

4, i. XSETAD 45

391 _ XSETBD

- GATET

‘a1>—

•v-

GATET 391 _ XSETDD

Figure 4-173. Fixed Memory Set Drivers and Return Circuits

4-371/4-372

ROPE DRIVER (CKT 40332)

+I3V 196 _

3PLMZDJ

# SELECTED BY ELECTRICAL TEST

APOLLO GUIDANCE AND NAVIGATION SYSTEM

ND-1021041

MANUAL

r

r

[B2I

f"

|48

|B22

[B23

r

[B24

|_B28

I -

-r

|B29

L

CORE ROPE S

CORE ROPE T

-

CORE ROPE R

—

I ROPE RESET RETURN (CKT 40352 )

| 6e] XRSTIN

i41	RSTRID 1	I'
f J	1 1 1	1 L
n	1 1	r
i4*	RSTR20 |	_ A
T i i J ! L

(CKT 40354)

Figure 4-174. Fixed Memory Reset Drivers and Return Circuits

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4-8. 6. 4. 6 Sense Amplifiers. Sixteen sense amplifiers are associated with fixed memory. These amplifiers operate similarly to those in erasable memory. The difference occurs in the input circuit (figure 4-175). The inputs to transformer T1 are returned to +3 vdc through resistors R1 and R2 to provide a return path for the sense lines. Output signals (40410A through 40417A and 40420A through 40427 A) are fed to register G through the sense amplifiers in erasable memory.

4-8.7 POWER SUPPLY. Power required for operation of the AGC is provided by two switching regulator circuits. The power supply functional block diagram is shown in figure 4-176, and consists of a +3 volt switching regulator, +13 volt switching regula¬ tor, filter circuits, and failure detection circuits.

4 -8.7.1 +3 Volt and +13 Volt Regulators Functional Description. The power switches and control circuits of the +3 volt and +13 volt regulators are identical. The voltage outputs are determined by minor circuit changes and the input from the control cir¬ cuits. The primary power input from the spacecraft is applied on two lines (A and B) through the primary power filter to the power switches of the +3 volt regulator. The outputs of both switches are tied together to produce an output designated +3A. The +3A output feeds some of the logic modules on tray A, the filter circuits, and the standby switch. Operation in the standby mode is described below. The dc level of +3 volts from the power switches is determined by the control circuits. A 51.2 kpps sync signal from the timer (PRSYNC) triggers a multivibrator in the control circuit, the output of which is of sufficient duration to produce 3 volts out of the power switch. The 3 volt output is regulated by feed-back of the +3A output into the control circuit.

The +2 8 A and +28B inputs to the power switches of the +3 volt regulator are com¬ bined to produce a +28 COM output, which energizes the +13 volt power switch. This circuit and its associated control circuit function in a manner identical to the +3 volt switching regulator. The output from this one power switch is designated B PLUS A. This output is applied to the oscillator, to the control circuit, to logic tray A, and to the standby switch. Inputs CNTRL 1 and CNTRL 2 to the +3 volt and +13 volt switch¬ ing regulators, respectively, allow simulated failure of the power supply under con¬ trol of the CTS during subsystem tests.

Rather extensive filtering occurs on the +3 and +13 volt outputs to the memory modules. The filters act essentially as isolation devices and are necessary to pre¬ vent the spurious signals that are generated in memory from being reflected into the power supply.

4 -8.7.2 Failure Detection Circuits Functional Description. The failure detection cir¬ cuit monitors the +3A and B PLUS A outputs and generates a power fail indication for an out-of-limits condition or complete failure of either output from the power supply. The low primary power detector generates signal STRT 1 which, when applied to the timer, causes a GOJAM condition if the +28 volt input falls below a predetermined level. The oscillator activity detector generates signal STRT 2 and assures an initial

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start sequence (GOJAM) until the oscillator starts running during a power-up condi¬ tion.

4 -8.7.3 +3 Volt Power Supply Detailed Description. The +3 volt power supply con¬ sists of control circuit A1 in module B12 and power switch modules B3 and B4. Pri¬ mary power (28 vdc) from the spacecraft is supplied on two lines (28 AUF, 28BUF) to the primary power filter circuit (figure 4-177). The filter outputs, +28A and +28B, are applied to power switches B4 and B3 respectively (figure 4-178). Two lines are used so that in the event that one line opens, primary power will still be supplied to the AGC. The two +28 volt inputs are combined in the power switch modules to form a +28 COM output which is used to power the control circuits (A1 and A 2), the power failure detection circuits, and the oscillator.

Transistors Q2 and Q3 in control circuit A1 form a free running multivibrator, the output of which is applied to the power switches through output stage Q4. The dc level supplied by the power switches is determined by the duty cycle of the signal from the multivibrator. The 51.2 kpps signal (PRSYNC), coupled to the base of Q2 through capacitor C5, fixes the frequency of the output pulses from the multivibrator. This input establishes the pulse width of the output (+3 PLS to the power switches) at 2.5 microsecond.

Transistor Ql in the control circuit is a differential amplifier which acts as a regulating device on the multivibrator. Zener diode CR2 establishes a constant refer¬ ence voltage at the base of Q1A. The +3 volt output is fed back to the base of QlB through the combination of C6 and R7. Any difference between the reference voltage applied to the base of QlA and the feedback voltage applied to the base of QlB affects the pulse width output of the multivibrator and opposes any change in the +3 volt out¬ put.

The control circuits for both the +3 volt and +13 volt regulators are identical. The level of the regulator output, either +3 or +13 volts, is established by resistor R2 and resistor R8. In the +3 volt regulator, R8 is connected in series with R9. In the +13 volt regulator, R8 is shunted out of the circuit.

The multivibrator output pulses are applied to transistor Ql in power switch modules B3 and B4. The output of Ql, applied through emitter follower Q2, charges the filter network (Cl, C2, C8, and L2) to a +3 volt level. The +28 volt primary input is filtered (C3-C6, LI) and applied to transistors Ql and Q2. The filter net¬ work prevents any ripple generated by the input pulses of the multivibrator from affecting the primary voltage supply.

Temperature sensing device R7 monitors the temperature of power transistors Ql and Q2, and provides temperature monitor signals (RD172, 173) to the spacecraft.

4 -8.7.4 +13 Volt Power Supply Detailed Description. The +13 volt power supply, fig¬ ure 4-179, consists of control circuit A2 in module B12 and power switch module B2.

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APOLLO GUIDANCE AND NAVIGATION SYSTEM	ND-1021041 MANUAL

Figure 4-175. Sense Amplifier and Voltage Source

4-377/4-378

4 0 3 56

Figure 4-176. Power Supply Functional Block Diagram

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05A7J2 1“ — |

Figure 4-177. Primary Power Filter

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The +28 COM line from power switch modules B3 and B4 is applied to the control cir¬ cuit and the power switch.

Operation of control circuit A2 is identical to circuit A1 in the +3 volt power sup¬ ply. The level of the multivibrator output, +13 PLS, is established by resistor R2 and by shunting resistor R8 out of the circuit.

Power switch module B2 is identical to modules B3 and B4 of the +3 volt supply and supplies an output of +13 volts (B PLUS A). The temperature of the power transistors is monitored by R7, and sent to the spacecraft as signal RD171.

4-8. 7. 5 Standby Mode. The standby mode of operation is controlled by the STBY/ON switch mounted at the front of the AGC. When placed in the STBY position, the +3 A and B PLUS A voltages applied to the switch contacts are interrupted, thus deener¬ gizing most of the AGC. As shown in figure 4-180. the +3A and B PLUS A voltages become +3B and B PLUS B respectively with the switch in the ON position. The +3B output powers all of the logic modules on tray A with the exception of the timer. This latter functional area is powered by the +3 A output. Thus, during standby all the logic modules except the timer (A28, A33, and A34) are disabled. The B PLUS B output powers three of the interface modules on tray A (A19, A20, and A39) and is applied to the filter circuits for use in the memory modules on tray B. Consequently, during standby there is no access to memory. However, the oscillator and power supply as well as interface module A40 are operative.

4-8. 7. 6 Filter-Circuits. The power supply filter circuits, figure 4-181, consist of several filters for power supplied to tray B, and capacitor filters for power supplied to most of the modules on tray A. Filtering circuits for the +3A output supplied to tray A are contained on the logic modules. The +3A output is applied to the circuitry for scalers A and B and the clock divider logic only. All other modules are powered by the +3B output with the exception of the interface modules (A19, A39; A20, A40).

4 -8.7.7 Failure Detection Circuits Detailed Description. The failure detection cir¬ cuits, figure 4-182, detect failures of the +3 volt and +13 volt power supply outputs. This includes an out-of-limits condition (either high or low) or complete failure of either power supply. In addition, a detector circuit monitors the primary input of +28 vdc in the event that this input is too low. The oscillator activity detector, is in¬ cluded in this funtional area since it is a function of the presence of outputs from the power supplies. The operation of this circuit is discussed below.

The power supply fail detection circuits include transistors Q5 through Q12 and associated circuitry. The +28 COM input from the power switch modules is dropped across the series combination of R19 and CR13, CR14 and CR15, and is applied as a reference voltage to differential amplifiers Q5 through Q8. Transistors Q5 and Q6 are the high and low limit detectors respectively for the +13 volt power supply. Tran¬ sistor Q5 conducts when the +13 volt output decreases to approximately +9 volts; transistor Q6 conducts when the +13 volt output increases. Transistors Q7 and Q8

4-382

+28 COM

APOILO GUIDANCE AND NAVIGATION SYSTEM

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+ 3A TO FILTERSLB3I )

ERAS DRIV(BIO.BII) CONTROL (BI2), ROPE MEM (B26, 27, 31), AND LOGIC TRAY A

RDI73

(TEMP MON 3)

Figure 4-178.

+ 3 Volt Power Supply

4-383/4-384

fpOWER SUPPLY CONTROL (CKT A2)

PRSYNC {51 2 KPPS FROM A20-A73)

(+I3PLS)

APOLLO GUIDANCE AND NAVIGATION SYSTEM	ND-1021041 MANUAL

l~POWER SWITCH B2

27

26

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B PLUS A TO OSC (B6), CONTROL (BI2), AND LOGIC TRAY A

RDI7I

(TEMP MON I)

40359

Figure 4-179. ^ 13 Volt Power Supply

4-385/4-380

APOLLO GUIDANCE AND NAVIGATION SYSTEM

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860

Figure 4-180. Standby Circuit

4-387

APOLLO GUIDANCE AND NAVIGATION SYSTEM

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are the high and low limit detectors respectively for the +3 volt power supply. Tran¬ sistor Q7 conducts when the +3 volt output increases to approximately +3.5 volts; Q8 conducts when the output decreases to approximately +2.5 volts.

Normally, transistors Q9 and Q10 are on, Oil is off and Q12 is on. The cur¬ rent flowing through Q12 energizes relay Kl. With K1 energized, the return circuit for the power fail indicators is open, and the indicators are not illuminated. When the output from either supply goes out of tolerance, one of the differential amplifiers turns on causing either Q9 or Q10 to cut off. This action causes Qll to turn on caus¬ ing Q12 to cut off. Relay Kl deenergizes closing the power fail indication circuit to the DSKY's. In addition, signal STRT1 is generated and is applied to the timer. This causes signal GOJAM to be generated.

The low primary power detector circuit monitors the +28 volt input. If this input drops too low, signal STRT1 is generated and causes signal GOJAM to fresh-start the AGC.

The oscillator activity detector (transistors Q5-Q7) assures the presence of sig¬ nal GOJAM during a power-up sequence or if the oscillator fails. After power turn¬ on, the oscillator output experiences some inherent delay. Consequently, the time counter does not start running until after the supply voltages reach their nominal values. Signal STRT2 is generated and is applied to the timer, and causes signal GOJAM. This condition exists until the clock starts running as indicated by signal Q2A from the clock divider section. Similarly, if the clock fails (assuming +13 volts is still present), Q2A is absent from the input to Q5. Signal STRT2 is generated and causes signal GOJAM.

4-8.8 MACHINE INSTRUCTIONS. Twenty-one different logical operations called machine instructions are performed on data within the AGC. Each instruction is a distinct operation such as add, increment the addressed counter, or multiply as de¬ fined by order codes or command signals in the sequence generator. Order codes are supplied from the central processor or generated with the sequence generator. The machine instruction is executed by sets of control pulses from the sequence gen¬ erator which regulate the flow of data through all functional areas except the DSKY’s. A set of control pulses is called an action; actions are generated at the rate of 1.024 megacycles, or every 0.977 microsecond. Twelve actions make one subinstruction and require one memory cycle time (MCT) for execution. An MCT is defined by timing pulses T01 through T12.

Machine instructions require from 1 to 16 MCT's for execution and contain as many subinstructions as there are distinct operations in the instruction. For ex¬ ample, the multiply instruction requires 8 MCT's to be executed but contains only three distinct operations. The first and last operations are executed once; the sec¬ ond operation is executed six times.

There are three functional divisions of machine instructions listed in table 4-XIX: regular, involuntary, and miscellaneous. Table 4-XX lists and defines those control pulses which are directly involved with the execution of a machine instruction. The

4-388

+ 3MXI

+ 3MX2

+ 3MYI

+ 3MY2

BPLMZI

BPLSIZI

(7

|B3I

APOILO GUIDANCE AND NAVIGATION SYSTEM

ND-1021041

MANUAL

J	1
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AI7.AI8	+38	+3B
A2I-A27 A29-A32 A35-A38	1 +3B	1 +3B
A28	+3A	+3A
A33.A34	+3A	+3A

NOTE ALL CAPACTORS ARE 6.8//F ALL CHOKES ARE BZ/iH

Figure 4-181. Power Supply Filter Circuits

4-389/4-390

APOLLO GUIDANCE AND NAVIGATION SYSTEM

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MANUAL

BPLSIW<>-

OVDC<^

(INTERFACE

CONNECTOR)

A3I/O0	A3I/I37
A 30/05	A30/I32
A35/I2	A35/I2
A35/I6	A35/I33
A35/IO	A35/I37

146

146

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SF026C

SF026S

SFI57T

SFI57C

POWER FAIL TO MAIN PANEL

POWER FAIL TO NAV PANEL

Figure 4-182. Power Supply Failure Detection Circuits

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MANUAL

Table 4-XIX. Machine Instructions

Initials	Purpose	Order Code	Subinstruction	Execution
		Entered		Time in
		Into Register SQ		MCT's
	REGULAR	INSTRUCTIONS
Basic Instructions
TC K	Transfer control to K	00	TC0	1
XCH K	Exchange data with location K	03	XCH0, STD2	2
CS K	Clear A and subtract data in K	14	CS0, STD2	2
TS K	Transfer data to K	15	TS0, STD2	2
MSK K	Mask (AND) with data from K	17	MSK0, STD2	2
AD K	Add data from Kand count on overflow or underflow	16	ADO, STD2	2
	In case of overflow		Also PINC	3
	In case of underflow		Also MINC	3
NDX K	Index (modify) next instruc¬ tion	02	NDX0, NDX1	2
CCS K	Count, compare, and skip with data at K	01	CCS0, CCS1	2
Extra Code Instructions
SU K	Subtract data from K and count on overflow or under¬ flow	13	SU0, STD2	4
	In case of overflow		Also PINC	5
	In case of underflow		Also MINC	5
MP K	Multiply with data at K	11	MP0, MP1, MP3	10
DV K	Divide by data at K	12	DV0, DV1, STD2	18

(Sheet 1 of 2)

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Table 4-XIX. Machine Instructions (cont)

Initials	Purpose	Order Code Entered Into Register SQ	Subinstruction	Execution Time in MCT's
INVOLUNTARY INSTRUCTIONS
Priority Program Instructions
RUPT	Interrupt program		RPT1, RPT3, STD2	3
RSM	Resume program		NDXO, RSM	2
Counter Instructions
PINC	Increment content of addressed counter		PINC	1
MINC	Decrement content of addressed counter		MINC	1
SHINC	Shift content of addressed counter		SHINC	1
SHANC	Shift content of addressed counter and add one		SHANC	1
MISCELLANEOUS INSTRUCTIONS
Start Instructions
GO	Computer GO		GO	1
TCSA	Start at specified address		TCSA	1
Display and Load Instructions
OTNC	Display content of address location		OINC	1
LINC	Load addressed location		LINC	1

(Sheet 2 of 2)

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Table 4-XX. Control Pulses

Pulse	Purpose
Cl	Forced-carry into bit position 1 of adder.
CLG*	Clear (reset) bit positions 16 and 14 through 1 of register G.
CTR	Decrements the multiply counter and sets stage 2 of state counter at action 12 when the content of the multiply counter goes to zero.
GP	Reset bit position 15 of register G and enter the new parity bit generated by the parity pyramid into it. If c(S) = 0014, reset bit position 15 of register OUT 4 and enter the generated parity bit there.
KRPT	Clears the request flip-flop (in interrupt priority control) that in¬ itiated program interrupt.
NISQ	Transfer the content of register B, bits 16 through 13, to regis¬ ter SQ at action 12.
RA	Read the content of register A into the write amplifiers.
RB	Read the content of register B into the write amplifiers.
RBI	Read 0 00001 (octal) into the write amplifiers.
RB2	Read 0 00002 (octal) into the write amplifiers.
RC	Read C output of register B into the write amplifiers.
RB14	Read 0 20000 (octal) into the write amplifiers (a logic ONE in bit position 14).
RG, RG*	Read the content of register G into the write amplifiers.
RLP	Read the content of register LP into the write amplifiers.
RP2	Reset bit position 15 of register G and enter c(P2) into it.
*The read (or write) signal generated is 1 microsecond long rather than 0.75 microsecond.

(Sheet 1 of 4)

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MANUAL

	Table 4-XX. Control Pulses (cont)
Pulse	Purpose
RRPA	Read the address provided by program interrupt priority control into the write amplifiers.
RS	Read the content of register S into the write amplifiers.
RSB	Read 1 00000 into the write amplifiers (minus zero is a logic ONE in write amplifier 16 only).
RSC	Read the content of the addressed flip-flop register onto the write amplifiers.
RSCT	Read the address provided by counter priority control into the write amplifiers.
RSTRT	Read STRT address into the write amplifiers.
RU, RU*	Read the content of adder output gates into the write amplifiers (1-15).
RUAC	Read bit position 16 of adder.
RZ	Read the content of register Z into the write amplifiers.
R1C	Read 1 77776 (octal) into the write amplifiers.
R22	Read 0 00022 (octal) into the write amplifiers.
R24	Read 0 00024 (octal) into the write amplifiers.
ST1	Set stage 1 of the state counter at action 12.
ST2	Set stage 2 of the state counter at action 12.
TMZ	Test for minus zero. Transfer the contents of the write am¬ plifiers to the sequence generator and set BR2 if all bits are logic ONE'S. Reset BR2 if all bits are logic ZERO' s.

♦The read (or write) signal generated is 1 microsecond long rather than 0.75 microsecond.

(Sheet 2 of 4)

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MANUAL

	Table 4-XX. Control Pulses (cont)
Pulse	Purpose
TOV	Test for overflow or underflow. Transfer the contents of write amplifiers 16 and 15 to the sequence generator and set BR2 in case of overflow or set BR1 in case of underflow. Reset BR1 and BR2 for other conditions.
TP	Test for correct parity.
TRSM	Test for resume. Transfer c(S) to the sequence generator and set stage 2 of state counter at action 12 if c(S) = 0025.
TSGN	Test sign. Transfer the content of write amplifier 16 to the se¬ quence generator and set BR1 if bit 16 is a logic ONE. Reset BR1 if bit 16 is a logic ZERO.
TSGN2	Test sign. Transfer the content of write amplifier 16 to the se¬ quence generator and set BR2 if bit 16 is a logic ONE. Reset BR2 if bit 16 is a logic ZERO.
TSGN3	Test sign. Transfer the content of write amplifier 16 to the se¬ quence generator and send signal to program interrupt priority control if bit 16 is a logic ONE.
WA	Clear register A and write the contents of the write amplifiers into register A.
WALP	Clear register A and bit position 14 of register LP.
WB	Clear register B and write the contents of the write amplifiers into register B.
WG	Clear bit positions 15 through 1 of register G and write the con¬ tents of the write amplifiers into register G.
WG*	Write contents of write amplifiers directly into bit positions 16 and 14 through 1 of register G and the parity bit into bit position 15.
WLP	Clear register LP and write the contents of the write amplifiers into register LP.

*The read (or write) signal generated is 1 microsecond long rather than 0.75 microsecond.

(Sheet 3 of 4)

4-397

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MANUAL

Table 4-XX. Control Pulses (cont)

Pulse	Purpose
WP, WP*	Enter the content in the write amplifiers into the parity logic.
WP2	Clear P2 in parity logic and enter the generated parity bit. If c(S) = 0014, reset bit position 15 of register OUT 4 and enter c(P2).
WS	Clear register S and write the contents of write amplifiers 12 through 1 into register S.
WSC	Clear the addressed flip-flop register and write the contents of the write amplifiers into it.
WX, WX*	Write the contents of the write amplifiers into register X.
WY, WY*	Clear registers X and Y and write the contents of the write am¬ plifiers into register Y.
WZ	Clear register Z and write the contents of the write amplifiers into register Z.
WOVI	Inhibit program interruption at end of current instruction in case of overflow or underflow.
wove	Increment or decrement OVCTR by executing PINC or MINC.
WOVR	Deliver counter overflow or underflow to the appropriate priority input selected by the content of register S.
♦ The read (or write) signal generated is 1 microsecond long rather than 0.75 microsecond.
(Sheet 4 of 4)

following paragraphs define each instruction in detail with the aid of instruction flow charts such as that shown in figure 4-183.

The fixed (F) and erasable (E) memories are shown combined on the charts. The central processor flip-flop registers are shown individually. Buffer-register B is shown with its direct (B) and its complement (C) side. The row marked M+l” sym¬ bolizes that circuitry of the adder which, on command, adds the quantity plus one to an operand entered into input register X or Y. The basic principle of operation of the adder is described as part of the central processor. The write amplifiers (WA’s) are symbolized by triangles placed into the flow lines. Registers are always signified by

4-398

APOLLO GUIDANCE AND NAVIGATION SYSTEM

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MANUAL

Figure 4-183. Subinstruction STD2 (Example for z > 0020)

4-399

APOLLO GUIDANCE AND NAVIGATION SYSTEM

ND-1021041

MANUAL

capital letters, their contents by small letters. Further, a means the complement of a. Control pulse symbols in parentheses indicate signals internal to the sequence generator (SQG). In the text, c(A) means the content of A, b(A) means the previous (before) content of (A). c(A) indicates the complemented c(A), and ce(A) indicates the edited c(A). In the box representing the sequence generator, action times are listed form 1 to 12. Each action time lists the control pulses generated by the sequence generator. Directly above each action time listing, the flow of information between the registers is shown. The AGC is performing no action when no control pulses are shown at an action time. Table 4 -XXI lists all the machine instructions and the control pulses generated at each action.

4-8.8. 1 Regular Instructions. Regular instructions identify distinct operations during program execution and consist of basic instructions and extra code instructions. Each basic instruction word in memory contains a three bit order code which identifies a basic instruction. This three bit order code is converted to a four bit order code within the central processor and then is supplied to the SQG. The three bit order code identifies eight basic instructions. Three additional regular machine instructions, the extra code instructions, are identified by order codes obtained within the central pro¬ cessor by indexing. Indexing adds selected quantities to quantities specified by the three bit order code. Therefore, the four bit order code sent to the sequence generator is not limited to identifying eight instructions. Eleven regular machine instructions, consisting of eight basic instructions and three extra code instructions, are identified.

A program consists of a series of basic instructions; extra code instructions are derived by modifying basic instructions. The relevant address of each basic instruc¬ tion is normally used to specify the location of the data to be worked with. The in¬ structions are stored at locations in numerical order to specify their sequence of execution. Therefore, the address of the instruction to be executed next (the next address) is defined by incrementing by one the address of the instruction presently being executed and storing it in register Z, the program counter. This is accom¬ plished during the execution of the basic instruction. If the normal sequence of ex¬ ecution is interrupted, the next address is stored in register Q for later use. Another duty of a basic instruction is to enter the entire code of the instruction to be executed next (the subsequent instruction) into register B. Finally, each regular instruction must enter the order code of the subsequent instruction into register SQ in order to initiate its execution.

4-8. 8. 1.1 Basic Instructions. There are eight basic instructions (table 4 -XIX), each of which consists of one or more subinstructions that are represented by order codes. The eight basic instructions are:

(1) Transfer control

(2) Count, compare, and skip

(3) Index

(4) Exchange

4-400

Table 4 -XXI. Control Pulse Timing for all Machine Instructions

APOLLO GUIDANCE AND NAVIGATION SYSTEM

ND-1021041

MANUAL

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APOLLO GUIDANCE AND NAVIGATION SYSTEM

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(Sheet 2 of 4)

Table 4 -XXI. Control Pulse Timing for all Machine Instructions (cont)

APOLLO GUIDANCE AND NAVIGATION SYSTEM

ND-1021041

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